Hitachi, Ltd.

Hiromitsu Maeda

Teruo Tanaka

Naoki Hamanaka

Tatsuo Higuchi

Shinichi Kawamoto

Tadayuki Sakakibara

Patrick Hamilton

A cache coherence control system for a multi CPU system having a plurality of CPU nodes, memory nodes and I/O nodes interconnected by a network. Each CPU node control circuit has an access right memory for managing an access right of the node in the unit of an extended node larger than a block size of the internal cache of a CPU. When a memory access is performed, the access right memory is referred to, and if the node has an access right to the extended block including a target block, the block is accessed without cache coherence control at other nodes.

CACHE COHERENT CONTROL SYSTEM FOR NETWORK NODES ALLOWS CPU OR I/O DEVICE TO ACCESS TARGET BLOCK WITHOUT CACHE COHERENCE CONTROL, IF ASSOCIATED NODE HAS ACCESS RIGHT IN AN ACCESS RIGHT MEMORY TO TARGET BLOCK

A parallel processor system has a plurality of nodes interconnected by a network for communication under control of a network interface controller of each node. The network interface controller includes a message reception controller for receiving a message from another node and judging illustratively the status of message reception and the need to return an acknowledge message; an acknowledge generating unit for generating an acknowledge message transmission request based on predetermined information in the message and the reception status when the return of an acknowledge message is judged to be necessary; and a message transmission controller for receiving an acknowledge the message transmission request and generating and returning an acknowledge message correspondingly. At the receiving node, the network interface controller can return an acknowledge message without processor intervention.

Parallel processor

Computer system

An arithmetic processing method and apparatus having first and second input registers and an arithmetic unit having a plurality of stages wherein an intermediate operation result of a previous iterative operation and input data are used to perform further iterative operations and obtain a final operation result as a vector sum. A serial number of input data is identified to check the order of the imputted data among a series of data to be processed. A control pattern to be used for control of the stages of the arithmetic processing unit is selected based on the identified serial number. The operation to be performed at each stage of the arithmetic processing unit is controlled in accordance with the selected control pattern, to obtain a final operation result to be outputted within a minimum number of operation cycles.

Arithmetic processing method and apparatus for performing arithmetic or

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Yokohama, Japan

Hiromitsu Maeda