Rohm Co., Ltd.

Tohoku Techno Arch Co., Ltd.

Hiromitsu Kimura

Yoshikazu Fujimori

Takaaki Fuchikami

Takahiro Hanyu

Takashi Nakamura

Hidemi Takasu

Toshiyuki Kanaya

Daisuke Notsu

Michitaka Kameyama

Yoshinobu Ichida

Masahide Tanaka

Takanori Ozawa

Jun Iida

Kazuhisa Ukai

Koji Nigoriike

Kazuya Ioki

Yuji Kurotsuchi

Kazutaka Miyamoto

Noriyuki Ema

A synchronous reset signal is generated from an asynchronous reset signal. The synchronous reset signal is output from the final-stage FF among L FFs connected in a cascade arrangement. A first error determination signal is output from the final-stage FF among M FFs connected in a cascade arrangement. Among N FFs connected in a cascade arrangement, the initial-stage FF receives the first error determination signal, and the final-stage FF outputs a second error determination signal. Based on the three outputs, the presence or absence of a fault in the circuit is determined. L, M, and N fulfil M≥2, L≥M+1, and M+N≥L+1.

Synchronous reset signal generation circuit and digital processing device

Disclosed is a semiconductor integrated circuit including a logic circuit, and a plurality of scan flip-flop circuits that hold input data or output data of the logic circuit and are capable of forming a scan chain for executing a scan test of the logic circuit. Each scan flip-flop circuit includes a scan data input part that receives input of scan data for the scan test, a normal data input part that receives input of normal data different from the scan data, and a data holding part capable of separately holding the normal data and the scan data.

Semiconductor integrated circuit

Disclosed is a flip flop circuit including a master latch circuit receiving master input data based on target input data, a slave latch circuit configured to load master output data from the master latch circuit and to hold the master output data, and a data output section, target output data based on the target input data being output from the data output section. The slave latch circuit includes a first to an N-th slave latch circuits provided in parallel with the master latch circuit (N is an integer of 2 or larger), the flip flop circuit further includes an output selection circuit selecting any one of data output from the first to N-th slave latch circuits, and selection data from the output selection circuit is output from the data output section as the target output data.

Flip flop circuit and data processing apparatus

Disclosed is a semiconductor memory device including a memory cell based on a static random access memory having a 6T or 4T2R configuration and including a first internal node, a second internal node, a first ferroelectric capacitor, and a second ferroelectric capacitor, the first ferroelectric capacitor and the second ferroelectric capacitor having respective first ends connected respectively to the first internal node and the second internal node. For recovering data stored in a non-volatile fashion in the first ferroelectric capacitor and the second ferroelectric capacitor, a first access transistor connected between the first internal node and a first bit line and a second access transistor connected between the second internal node and a second bit line are turned on, and respective capacitive components of the first bit line and the second bit line are used as load capacitances.

Semiconductor memory apparatus

A data processing apparatus includes: a plurality of power supplies; a nonvolatile logic configured to be driven with power output from the plurality of power supplies; and a plurality of detection parts configured to detect output states of the plurality of power supplies, wherein the nonvolatile logic performs data processing based on a result of the detection of the plurality of detection parts.

Data processing apparatus, structure and power generation apparatus including the same

A data holding devicehas an inverter loop, a differential pair circuitconnected to the ground terminals of inverters, a first potential setterconfigured to turn the output terminals of the inverters to a first potential (VDD), and a second potential setterconfigured to turn the ground terminals of the inverters to a second potential (VSS). During data holding, the differential pair circuitand the first potential setterare disabled so that the ground terminals of the inverters are at the second potential. During data writing, the differential pair circuitis disabled so that the output terminal of one inverter is at the first potential and the ground terminal of the other inverter is at the second potential.

Data holding device, nonvolatile data holding device, and data reading method

A data retention control circuit includes a data retention part having first and second logic circuits, a ferroelectric storage part having first and second ferroelectric device parts, first and second transmission control parts, and a test voltage supply control part. The first transmission control part has first and second transmission control circuits controlling first and second logic signals to the first and second ferroelectric device parts, respectively. The second transmission control part has third and fourth transmission control circuits controlling transmission of first and second storage data from the first and second ferroelectric device part to the second and first logic circuits, respectively. The test voltage supply control part has first and second test voltage supply control circuits controlling supplies of first and second test voltages to the second and first logic circuit, respectively.

Data retention control circuit, data writing method, data reading method, method of testing characteristics of ferroelectric storage device, and semiconductor chip

A counter includes: a count processing circuit including a nonvolatile register; a regulator receiving voltage from a direct current power supply, generating power supply voltage based on the received voltage for the count processing circuit, and supplying the power supply voltage to the count processing circuit; and a delay circuit receiving the power supply voltage and supplying a count signal to the count processing circuit after the power supply voltage is supplied to the count processing circuit. After having received the power supply voltage from the regulator, the count processing circuit updates a count value in response to the count signal and holds the updated count value in the nonvolatile register in a non-volatile manner.

Electronic circuit and electronic device including the same

Provided is a nonvolatile storage gate embedded logic circuit embedding a nonvolatile storage gate which can hold data after power supply cutoff and can cut off a power supply at the same time shifting into a standby state. The nonvolatile storage gate embedded logic circuit includes a logic calculation unit having a logic gate, and a nonvolatile storage gate having a nonvolatile storage element, a data interface control unit disposed so as to be adjoining to the nonvolatile storage element, and receiving a nonvolatile storage control signal for data read-out from the nonvolatile storage element and data write-in to the nonvolatile storage element, and a volatile storage element disposed so as to be adjoining to the nonvolatile storage element, receiving a data input signal and a clock signal, and outputting a data output signal.

Nonvolatile storage gate, operation method for the same, and nonvolatile storage gate embedded logic circuit, and operation method for the same

A data holding device includes a loop structure unit configured to hold data using a plurality of logic gates connected in a loop shape, a nonvolatile storage unit including a plurality of ferroelectric elements, the nonvolatile storage unit configured to store the data held in the loop structure unit in a nonvolatile manner using hysteresis characteristics of the ferroelectric elements, and a circuit separation unit configured to electrically separate the loop structure unit and the nonvolatile storage unit. The ferroelectric elements of the nonvolatile storage unit are surrounded by a dummy element smaller in width than the ferroelectric elements.

Data holding device and logic operation circuit using the same

A control circuitincludes an internal clock generating portion (), which starts generating an internal clock signal (LCLK) required by a control portion () to perform action when a specific signal pattern appears in a trigger signal, continually generates the internal clock signal (LCLK) at least before the control portion () completes predetermined processing, and then stops generating the internal clock signal (LCLK); and the control portion (), which uses the internal clock signal (LCLK) to perform the predetermined processing.

Control circuit and data hold device using the control circuit

A data holding device according to the present invention includes a loop structure portion LOOP for holding data using a plurality of logic gates (NANDand NAND) connected in a loop, a nonvolatile storage portion (NVM) for storing in a nonvolatile manner the data held in the loop structure portion (LOOP) by using the hysteresis characteristics of ferroelectric elements, a circuit separating portion (SEP) for electrically separating the loop structure portion (LOOP) and the nonvolatile storage portion (NVM), and a set/reset controller (SRC) for generating a set signal (SNL) and reset signal (RNL) based on data stored in the nonvolatile storage portion (NVM), wherein the plurality of logic gates are each set and reset to an arbitrary output logic level in accordance with the set signal (SNL) and reset signal (RNL).

Data holding device

The electronic device according to the present invention comprises a power supply; a processing section which has a nonvolatile register and performs predetermined processing by inputting and outputting data to and from the nonvolatile register on the basis of power fed from the power supply; an external signal inputting section for inputting an external signal to the processing section; and a power feed control section, which interrupts power feeding from the power supply to the processing section, while maintaining responsiveness to the external signal in a state in which the processing state of the processing section is stored in the nonvolatile register, and resumes power feeding from the power supply to the processing section in response to the external signal.

Growing community of inventors

Kyoto, Japan

Hiromitsu Kimura