Tokyo Electron Limited

Hiromitsu Kambara

Lee Chen

Toshihisa Nozawa

Akiteru Ko

Hongyu Henry Yue

Tetsuya Nishizuka

Hiromasa Mochiki

Caizhong Tian

Masaaki Hagihara

Nobuhiro Iwama

A method for etching a high-k dielectric layer on a substrate in a plasma processing system is described. The high-k dielectric layer can, for example, comprise HfO. The method comprises elevating the temperature of the substrate above 200&#xb0; C. (i.e., typically of order 400&#xb0; C.), introducing a process gas comprising a halogen-containing gas, igniting a plasma from the process gas, and exposing the substrate to the plasma. The process gas can further include a reduction gas in order to improve the etch rate of HfOrelative to Si and SiO.

Method and system for etching a high-k dielectric material

A plasma processing system for treating a substrate includes a processing chamber including a first chamber portion configured to receive a first gas for providing a plasma space, and a second chamber portion configured to receive a second gas for providing a process space having process chemistry to treat the substrate. A substrate holder is coupled to the second chamber portion of the processing chamber, and configured to support the substrate proximate the process space, and a plasma source is coupled to the first chamber portion of the processing chamber, and configured to form a plasma in the plasma space. A grid is located between the plasma space and the process space, and configured to permit the diffusion of the plasma between the plasma space and the process space in order to form the process chemistry from the process gas.

Plasma processing system for treating a substrate

A method and processing tool are provided for trimming a gate electrode structure containing a gate electrode layer with a first dimension. A reaction layer is formed through reaction with the gate electrode structure. The reaction layer is the selectively removed from the unreacted portion of the gate electrode structure by chemical etching, thereby forming a trimmed gate electrode structure with a second dimension that is smaller than the first dimension. The trimming process can be carried out under process conditions where formation of the reaction layer is substantially self-limiting. The trimming process can be repeated to further reduce the dimension of the gate electrode structure.

Method of trimming a gate electrode structure

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Hiromitsu Kambara