Hitachi, Ltd.

Other

Hiromitsu Imori

Toshihiko Kurihara

Kenji Matsubara

Hiroshi Nakamura

Hideo Wada

Kisaburo Nakazawa

An information processing system which includes a main memory, a processing unit which executes a prefetch instruction included as one of a plurality of instructions of a program in the main memory, an internal cache controlled as a first level cache, and a cache control function which controls an external cache external of the processing unit as a second level cache. The prefetch instruction, when executed, causes the processing unit to selectively perform a prefetch operation by transferring operand data to be used in a subsequent load instruction from the main memory to the first and second level caches or the second level cache only, prior to executing the subsequent load instruction. The prefetch instruction includes a plurality of indication bits for specifying cache levels to which the operand data is to be transferred.

Processing device with prefetch instructions having indicator bits specifying cache levels for prefetching

An information processing system includes a processing unit which executes a prefetch instruction included as one of a plurality of instructions of a program in a main memory two hierarchical level caches connected to the processing unit and the main memory as arranged so that a primary cache close to the processing unit is a first level cache, and a secondary cache close to the main memory is a second level cache. The prefetch instruction, when executed, causes the processing unit to perform a prefetch operation by transferring operand data to be used in a subsequent load instruction from the main memory to the two hierarchical level data caches, prior to executing the subsequent load instruction. The prefetch instruction includes a plurality of indication bits for specifying cache levels to which the operand data is to be transferred.

An information processing system including a processing device for controlling hierarchical level data cache memories in response to execution of a prefetch instruction. The prefetch instruction includes indication bits for indicating a quantity of an operand data to be transferred from a main memory to an external cache, each being external of the processing device. The transferred operand data is used in a subsequent load instruction from the main memory to the external cache only, not to the internal cache, prior to executing the subsequent load instruction.

Information processing system with prefetch instructions having indicator bits specifying a quantity of operand data for prefetching

A processing device for controlling hierarchical level data cache memories in response to execution of a prefetch instruction. The prefetch instruction includes indication bits for indicating a quantity of an operand data to be transferred from a main memory to an external cache, each being external of the processing device. The transferred operand data is used in a subsequent load instruction from the main memory to the external cache only, not to the internal cache, prior to executing the subsequent load instruction.

Processing device which prefetches instructions having indicator bits specifying cache levels for prefetching

An information processing unit and method for controlling a cache according to a software prefetch instruction, are disclosed. Indication bits are provided for indicating a hierarchical level of a cache to which an operand data is to be transferred or a quantity of an operand data to be transferred, or both. The indication bits are provided in a software prefetch instruction such that at the time of a transfer of block data or line data, a required data is transferred to a cache based on the indication bits in the prefetch instruction. Thus, it is not necessary to change the timing for executing a software prefetch instruction depending on which one of the caches of the hierarchical levels is hit, and a compiler can generate an instruction sequence more easily.

Information processing system with prefetch instructions having indicator bits specifying cache levels for prefetching

An information processing unit and method for controlling a cache according to a software prefetch instruction, are disclosed. Indicator or indication bits are provided for indicating a hierarchical level of a cache to which an operand data is to be transferred or a quantity of an operand data to be transferred, or both. The indication bits are provided in a software prefetch instruction such that at the time of a transfer of block data or line data, a required data is transferred to a cache based on the indication bits in the prefetch instruction. Thus, it is not necessary to change the timing for executing a software prefetch instruction depending on which one of the caches of the hierarchical levels is hit, and a compiler can generate an instruction sequence more easily.

Information processing unit and method for controlling a hierarchical

A plurality of physical registers greater in number than can be addressed by instructions are provided. The physical registers are divided into a plurality of partial groups or windows. Each of the physical registers is specified by a physical register number determined by a combination of the number of the window and a register number contained in the window. The window number is indicated by a current floating point window pointer stored in a current floating point window pointer register. In executing a vector calculation program having repetitive loops of an instruction sequence, the window is changed for each loop by changing the value of the current floating point window pointer. Vector data to be calculated at the i-th loop is read from a main memory at the loop before the i-th loop. The calculated result of the vector data at the i-th loop is stored in the main memory at the loop after the i-th loop, thereby eliminating performance degradation to be caused by a slow data read time and improving the operation speed.

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Hadano, Japan

Hiromitsu Imori