Kioxia Corporation

Hiromitsu Harashima

Yasushi Kameda

Yoshiko Kato

Yuuichi Tatsumi

Naoyuki Kondo

Tsutomu Takahashi

Shinichi Maruyama

A semiconductor device according to an embodiment includes a semiconductor chip, a semiconductor element, a stacked body, and a structure body. The semiconductor chip includes a first surface, a second surface, and a side surface between the first surface and the second surface. The semiconductor element is provided in the center of the semiconductor chip when viewed from the normal direction of the first surface. The stacked body is provided at the outer peripheral end portion of the semiconductor chip when viewed from the normal direction and includes a plurality of first layers and a plurality of second layers alternately stacked in the normal direction. The structure body is provided in at least a part between the semiconductor element and the side surface when viewed from the normal direction and extending from a position higher than the stacked body to a position lower than the stacked body.

Semiconductor device

A semiconductor wafer according to the present embodiment is a semiconductor wafer having a first face. A plurality of chip structures are provided on a plurality of chip regions of the first face. A test structure is provided on dicing regions between adjacent ones of the chip regions. The chip structures each comprise first integrated circuits provided on the semiconductor wafer, and a first stacked body provided above the first integrated circuits and including a plurality of first layers and a plurality of second layers different from the first layers alternately stacked. The test structure comprises second integrated circuits provided on the semiconductor wafer, and a second stacked body provided above the second integrated circuits and including the first layers and the second layers alternately stacked.

Semiconductor wafer, semiconductor chip, and dicing method

A semiconductor storage device includes first and second chips. The first chip includes memory cells provided on a first substrate in a memory cell region, a plurality of first pads provided on a first surface of the first substrate and disposed in an edge region of the first chip that surrounds the memory cell region, and a first conductive layer provided on the first substrate and electrically connected to the first pads. The second chip includes a first circuit provided on a second substrate in a circuit region, a plurality of second pads provided on the second substrate and disposed in an edge region of the second chip that surrounds the circuit region, and a second conductive layer provided on the second substrate and electrically connected to the second pads. The first pads of the first chip and the second pads of the second chip are bonded facing each other.

Growing community of inventors

Yokohama Kanagawa, Japan

Hiromitsu Harashima