Hitachi, Ltd.

Renesas Electronics Corporation

Other

Hitachi Medical Corporation

Mitsubishi Denki Kabushiki Kaisha

Renesas Technology Corp.

Kasei Optonix, Ltd.

Hitachi Metals, Ltd.

Brother Industries, Ltd.

Hitachi Car Engineering Co., Ltd.

Mitsubishi Electric Engineering Company, Limited

Hitachi Engineering Co., Ltd.

Yamada Atomizer Company Limited

Hiromichi Yamada

Nobuyasu Kanekawa

Fumio Murabayashi

Tatsumi Yamauchi

Kotaro Shimamura

Minoru Yoshida

Takashi Hotta

Yuichi Ishiguro

Kesami Hagiwara

Tsutomu Yamada

Teruaki Sakata

Atsushi Suzuki

Hideki Kohno

Kohei Sakurai

Masahiro Matsumoto

Keiji Hanzawa

Yoji Nishio

Yasuhiro Nakatsuka

Teppei Hirotsu

Takanaga Yamazaki

Katsunori Koike

Yoshikazu Kiyoshige

Hideo Hara

Ichiro Miura

Yoko Uchida

Kayoko Nemoto

Kosaku Hirose

Hajime Yamamoto

Atsushi Miyazaki

Teruki Suzuki

Yasuhiko Uehara

Makoto Sato

Yasutsugu Tsutsumi

Yutaka Morita

Sueyoshi Tanaka

Dai Fujii

Yasukazu Morita

Tatsuro Takahashi

Shigeru Matsuo

Takashi Miyamoto

Masatoshi Shiiki

Yuichiro Morita

Takashi Hase

Yukio Hashiguchi

Tadashi Fukushima

Shinji Murai

Masaaki Komatsu

Shin Imamura

Takeshi Kataoka

Hidetsugu Matsukiyo

Yoichi Yuyama

Hidehito Takewa

Satoshi Tanaka

Tatsuki Inuduka

Mitsuhiro Matsuzaki

Takaaki Kobiki

Tooru Komagawa

Shigeo Fujino

Akihiro Yamate

Noriyasu Ido

Syoji Yoshida

Tsuneyuki Kanai

Susumu Omatoi

Hitoshi Suzuki

Koyo Katsura

Yusuke Kanno

Masatoshi Hoshino

Hideo Maejima

Yuichi Abe

Masaki Ojima

Ryo Fujita

Osamu Miyazaki

Takashi Kawana

Shigeya Tanaka

Tadanobu Toba

Kenji Maio

Fumio Kawaguchi

Naoki Yada

Kenichi Shimbo

Hideo Sawamoto

Michio Ito

Tatsuya Maruyama

Shunichi Iwata

Eiki Kamada

Keiji Umetani

Choichiro Okazaki

Mitsuyasu Kido

Hiroshi Takagi

Yoichi Oba

Kunio Kobayashi

Kazumi Hatayama

Hideji Aoki

Hideji Fujii

Yoshimasa Hara

Yasuo Sugure

Shinji Semba

Manabu Nakagawa

Kouichi Koike

Yasuo Tsukuda

Kazunori Hikone

An object of the present invention is to propose a partial discharge determination device and method that can highly reliably determine the degree of progress of partial discharge occurring in an underground power transmission cable without preparing plural standard patterns. A distribution pattern of a set of the charge amount and the occurrence phase angle of each partial discharge occurring in a period of one or more cycles of an applied voltage of a power transmission cable is sequentially generated, a first classification process in which the pattern is classified into any one of classes on the basis of a standard distribution pattern for each class and a second classification process in which the distribution pattern are executed, a classification result by the first classification process is evaluated on the basis of a classification result by the second classification process, and the degree of progress is determined.

Partial discharge determination device and method

Data on a memory space are compared without using a CPU, and an interrupt is generated in an interrupt condition based on at least one of the number of times of the comparison and the number of times of coincidence with a comparison condition. An interrupt controller outputs an interrupt signal to a first CPU core or a second CPU core. A DMAC transfers data on the memory space to at least one of a first buffer and a second buffer. A comparison circuit compares the data of the first buffer with the data of the second buffer. A condition coincidence frequency counter counts the number of times at which the comparison in the comparison circuit coincides with a comparison condition. An interrupt request circuit outputs an interrupt request to the interrupt controller, based on at least one of a value of the condition coincidence frequency counter and a value of a comparison frequency counter.

Semiconductor integrated circuit device and method for comparing data

Provided is an integrated circuit or the like capable of rapidly correcting erroneous data write and making contents of the RAMs that are in the multiple modular redundancy coincident in a case where a logic circuit performs the erroneous data write to the RAMs while operating logic circuits and RAMs at a high speed. In order to solve the problem, the integrated circuit including logic circuits and RAMs for which data write and data read are performed by the logic circuits includes a multiple modular redundancy logic circuits, a plurality of RAMs respectively connected to the multiple modular redundancy logic circuits, and a RAM access correction unit which compares access signals from the multiple modular redundancy logic circuit to the RAMs to detect an erroneous data write and corrects an error of the RAM.

Integrated circuit and programmable device

In a system for performing clock generation for each semiconductor device, synchronization between the semiconductor devices is achieved without causing a count value in a counter to be discontinuously changed. A semiconductor deviceincludes a clock oscillator, a counterconfigured to count the number of clocks, a periodic registerin which a value corresponding to a period for synchronization is set, a comparison circuitconfigured to compare the count value in the counterwith the set value in the periodic register, a match flag registerin which a predetermined value is set when the count value coincides with the set value, a match output terminalconfigured to output the value in the match flag registerfrom the own semiconductor device, a match input terminalto which a value output from another semiconductor device to be synchronized is input, and a reset circuit configured to reset the counterand the match flag registerwhen both the value in the match flag registerof the own semiconductor device and the value input to the match input terminalbecome a predetermined value.

Semiconductor device, control system, and synchronization method

The present invention aims to provide a programmable device with a configuration memory that can hold the state of the occurrence abnormal situation that is difficult to assume such as a failure occurring in the programmable device due to the terrestrial radiation of the configuration memory, even during power off, in order to improve the reproducibility in device testing based on the held error information. The programmable device with the configuration memory includes: an error detection section for detecting an error in the configuration memory, and outputting the detected error as well as an address in which the error occurred, as error information; and an error information holding section provided with a non-volatile memory to store the output error information.

Programmable device, error storage system, and electronic system device

Provided are a communication processing device and a communication system, capable of securely updating a communication protocol process with a simple configuration and technique, while continuing communication. A communication processing device, which is connected to a communication network, includes a programmable logic device in which partial rewriting of a logic circuit is possible, during an operation of a host device in the communication network, in which the programmable logic device includes at least two communication processing circuits of which each performs a communication protocol process, and in which one communication processing circuit is operable due to switching, a first communication processing circuit performs communication, and a second communication processing circuit is on standby, updating means for downloading logic circuit data of an updated communication protocol process, from the communication network, and performing a circuit configuration for the second communication processing circuit, a flag that indicates whether or not the circuit configuration for the second communication processing circuit is finished, and by which a circuit configuration state is able to be read to the host device side through communication, and a register that is intended for switching to any one communication processing circuit to be used, and is writable from the host device side through communication.

Communication processing device, communication method, and communication system

First data to be written which is output from a function module () is supplied to a built-in memory () and a first buffer memory (), and second data to be written which is output from the function module () is supplied to the built-in memory () and a second buffer memory (). The first and second FIFO memories () select and store data items having a predetermined number of outputs from a plurality of first and second output data items which are sequentially output from the first and second buffer memories (), and do not select other data items. A comparator () compares the data items having the predetermined number of outputs which are selected and are output by the first and second FIFO memories () with each other.

Semiconductor integrated circuit and method for operating same

A microcontroller includes a central processing unit, a PWM signal generation unit which generates a PWM signal according to a generation condition of a PWM signal set by the central processing unit, and a diagnostic unit which inputs the generated PWM signal therein and detects a pulse period and a pulse width, based on the input signal and which determines whether the detected pulse period and pulse width respectively coincide with a pulse period and a pulse width corresponding to the generation condition.

Microcontroller, control device and determination method

To have a problem of occurrence of the same failure in failure detection of a microcontroller. A microcontroller has a CPU and a data access control circuit. The data access control circuit performs two types of accesses: an individual access in which a data access of the CPU is performed for each thread, and a shared access in which a data access of the CPU is performed by executing two threads. The data access control circuit detects a failure of the CPU by making a comparison between the command and the address, respectively, in the shared access generated by executing the two threads.

Semiconductor integrated circuit device and microcontroller

The present invention provides a semiconductor integrated circuit device realizing improved detection of a failure while suppressing deterioration in performance. In a semiconductor integrated circuit device executing a plurality of threads while switching them synchronously with clocks, registers used for executing the threads are provided for the respective threads. Programs independent of each other and the same program as the threads are executed while being switched. In the case of executing the same program by a plurality of threads, a comparison circuit for comparing results of execution using registers provided in correspondence with the threads is provided.

Comparison for redundant threads

A microcontroller capable of improving processing performance as a whole by executing different programs by a plurality of CPUs and capable of detecting abnormality for safety-required processing by evaluating results of the same processing executed by the plurality of CPUs. A plurality of processing systems including CPUs and memories are provided, data output from the CPUs in each of the processing systems is separately compressed and stored by compressors for each of the CPUs, respectively. The compressed storage data is mutually compared by a comparator, and abnormality of processing can be detected when the comparison result indicates a mismatch. Even when the timings by which the same processing results are obtained are different when the plurality of CPUs asynchronously execute the same processing, the processing results of both of them can be easily compared with each other since compression is carried out by the compressors. Moreover, since the comparison of the comparator is enabled when comparison enable is given from all the CPUs, the comparison operation result can be obtained based on the timing at which the results of compression by the plurality of compressors are determined.

Multi-core microcontroller having comparator for checking processing results

A microcontroller in which respective CPUs execute different applications so as to improve processing performance, and the respective CPUs execute an application that requires safety and mutually compare the results thereof so as to enhance the reliability of write data is provided. The microcontroller has a plurality of processing systems made up of a first CPU, a second CPU, a first memory and a second memory, and for the instruction processing about specific processing set in advance, the write to peripheral modules which are not multiplexed is executed twice, and the write data of the first time and the second time are mutually collated.

Microcontroller and electronic control unit

A computer system which shortens standby time of CPUs and improves CPU processing efficiency of a performance mode upon switching from the performance mode (parallel operation) to a safety mode (master/checker operation) is provided. In a computer system including: at least two CPUs; a programmable interrupt controller for interrupting the CPUs; and a comparator for mutually comparing outputs of the CPUs, switching between the performance mode of executing mutually different processes by the CPUs, respectively, to improve performance and the safety mode of executing mutually the same processes by the CPUs and collating results by the comparator to detect failure can be carried out; CPUs to be interrupted can be set for each interrupt factor; and whether the performance mode is to be executed or the safety mode is to be executed can be set for each interrupt factor.

Computer system including an interrupt controller

Multi-core microcontroller having comparator for checking processing result

Growing community of inventors

Hitachi, Japan

Hiromichi Yamada