Renesas Technology Corp.

Renesas Electronics Corporation

Hitachi Engineering Co., Ltd.

Renesas Northern Japan Semiconductor, Inc.

Hitachi Hokkai Semiconductor Ltd.

Hiromichi Ishikura

Toyohiro Shimogawa

Katsumasa Uchiyama

Shoichiro Chiba

Naoki Handa

Masaru Takahashi

Naoki Yada

Hirofumi Mukai

Toru Ichien

Toshihiro Matsuo

Tatsuo Nishino

Gou Teshima

Jyunji Ishikawa

A data processing device includes: a first power-on reset circuit; a second power-on reset circuit with higher power consumption and higher reset voltage accuracy than the first power-on reset circuit; a storage unit storing information for determining whether to keep the second power-on reset circuit in an active state or an inactive state; and a central processing unit initialized in response to respective outputs of the first and second power-on reset circuits and setting the information in the storage unit.

First power-on reset circuit with higher power consumption than a second power-on reset circuit

A semiconductor integrated circuit has an internal circuit to which operation power is supplied or interrupted, and a power supply control circuit for controlling the supply and interruption of operation power to the internal circuit in accordance with an operation mode. The power supply control circuit has a storage circuit and a power supply control sequence circuit. The storage circuit inputs and holds switching instruction data for instructing switching between supply and interruption of the operation power and low-power-consumption-mode data determining an operation mode of the interruption of operation power and cancellation of the interruption. The power supply control sequence circuit performs a control of transition between the interruption and supply of the operation power with reference to the switching instruction data and the low-power-consumption-mode data held in the storage circuit and, at the time of cancelling a state of interrupting the supply of operation power in response to the switching instruction data in the operation power supply interruption state according to the low-power-consumption-mode data, stops newly referring to the low-power-consumption mode data until an operation of the internal circuit to which the operation power is to be supplied is assured.

Semiconductor integrated circuit device having internal circuit with plural power supply regions

Semiconductor integrated circuit

A data processor including a central processing unit and a data transfer control unit is disclosed. The data transfer control unit has an address register for storing a transfer address. The data transfer control unit transfers data according to a transfer unit size selected from a plurality of transfer unit sizes. If the address register contains an odd address as an initial value, the data transfer control unit transfers data according to a different transfer unit size that is smaller than the selected transfer unit size. If the data transfer control unit determines that a remaining quantity of data to be transferred is smaller than the selected transfer unit size, the selected transfer unit size is switched to a smaller transfer unit size selected from the plurality of transfer unit sizes.

Data transfer control unit with selectable transfer unit size

A process program such as an erasing/programming program is stored in a boot mat in a nonvolatile memory operational in a boot mode specified after reset start, and a transfer control program for the process program is also stored therein in advance. With an action of setting control information to a predetermined register as trigger, the state of an on-chip CPU is changed from placed in execution of an optional user program to enabled for execution of a transfer control program in the boot mat, and the CPU is returned to the re-execution state of the optional program, after the process program is transferred to an on-chip RAM.

Microcomputer and data processing device

Growing community of inventors

Tokyo, Japan

Hiromichi Ishikura