Mitsubishi Denki Kabushiki Kaisha

Renesas Electronics Corporation

Renesas Technology Corp.

Hiromi Notani

Harufusa Kondoh

Masahiko Ishiwaki

Yoshio Matsuda

Yoshihiko Yasu

Yasunobu Nakase

Takashi Yamaki

Tsutomu Yoshimura

Isamu Hayashi

Hideaki Yamanaka

Akira Oizumi

Soichi Kobayashi

Takayuki Fukuoka

Kazuyoshi Oshima

Hiroshi Makino

Naoya Watanabe

Hideki Ando

Yoshikazu Morooka

Hirotoshi Yamada

Issei Kashima

Hirotaka Saito

Munenori Tsuzuki

Ryuji Mano

Takahiro Shimada

A data processing device includes a load circuit including a central processing unit and operated by supplied electric power, a step-down power supply circuit stepping down an external power supply voltage and including an output node coupled to the load circuit, the step-down power supply circuit including a first step-down unit stepping down the external power supply voltage, and a bias current control circuit controlling a magnitude of bias current flowing through an auxiliary path from the output node to a ground, the auxiliary path is separate from a path to the load circuit, and a control circuit increasing the magnitude of the bias current, prior to a change of an operation state of the load circuit by which a relatively large change occurs to an amount of current consumed by the load circuit.

Data processing device and data processing system

A semiconductor device having an active mode and a standby mode as operation modes, includes a first power supply line supplied with a first internal power supply voltage from a first external power supply and an internal power supply circuit generating a second internal power supply voltage based on an external power supply voltage from a second external power supply circuit. A second power supply line supplied with said second internal power supply voltage from said internal power supply circuit.

Semiconductor device having active mode and standby mode

In an active mode, a VDD line receives an internal power supply voltage from an external regulator. A VDD_RAM line receives an internal power supply voltage from an internal regulator. A PMOS switch includes a first PMOS transistor having a source and an N-type well connected to the VDD line, and a second PMOS transistor having a source and an N-type well connected to the VDD_RAM line and a drain connected to a drain of the first PMOS transistor. The first PMOS transistor is controlled based on a control command from a system control circuit and a voltage of the VDD_RAM line. The second PMOS transistor is controlled based on the control command and a voltage of the VDD line.

A step down unit steps down an external power supply voltage Vcc. A bias current control circuit controls the magnitude of bias current flowing through an auxiliary path connecting an output node and the ground. A system controller increases the magnitude of the bias current, prior to a change of the operation state of a load circuit by which a relatively large change occurs to the amount of current consumed by the load circuit including a central processing unit.

There is provided a regulator circuit capable of increasing the capacity of the output transistor for supplying current, stably generating an internal power supply voltage and adapting to the reduction of a power supply voltage. The regulator circuit includes an output transistor which is supplied with an external power supply voltage and supplies dropped voltage to an internal circuit, a differential amplifier for outputting a gate potential applied to the gate of the output transistor, a reference voltage generating circuit for supplying a reference voltage to the differential amplifier, and a cut-off transistor for turning off the output transistor to stop supplying power to the internal circuit. The output transistor is comprised of a depression NMOS transistor whose threshold voltage is a negative voltage. The regulator circuit further includes substrate potential control means for controlling the substrate potential of the depression NMOS transistor.

Regulator circuit

The present invention provides a semiconductor chip which is insusceptible to noise and whose consumption current is small. In a semiconductor chip, an internal power supply voltage for an internal circuit block is generated by a regulator having small current drive capability and a regulator having large current drive capability. A voltage buffer is provided between a reference voltage generating circuit and the regulator having large current drive capability. In a low-speed operation mode, the voltage buffer and the regulator having large current drive capability are made inactive. Therefore, noise in reference voltage is suppressed, and consumption current can be reduced.

Semiconductor chip

A data storage circuit having a plurality of memory cells (S), a plurality of bit lines (BL, /BL) and a precharge circuit further comprises a discharge circuit. In an operating mode of the data storage circuit, the bit lines (BL, /BL) are precharged by the precharge circuit under the control on the basis of a chip enable signal (CE) before write or read of data into/from the memory cells (S) and in a standby state, the bit lines (BL, /BL) are discharged by the discharge circuit. Further, also in a sleep mode, the bit lines (BL, /BL) are discharged by the discharge circuit. With this circuit configuration and operation, it is possible to provide the data storage circuit which allows reduction in standby power consumption by suppressing standby currents in the standby state.

Data storage circuit

A semiconductor integrated circuit device is provided, in which a node from which an output signal of a level shifter is sent can be initialized such that the potential thereof be set at a desired logic level at the time of power supply. The semiconductor integrated circuit device includes a level shifterand two capacitors Nand C. The level shifterreceives an input signal and converts the received signal to a signal having a voltage amplitude greater than that of the received signal, then to provide the signal to a node D. The capacitor Nis connected to the node D, and the capacitor Cis connected in series with the capacitor N. The capacitor Nis formed of a MOS transistor having a gate connected to the node Dand a source and a drain both connected to the capacitor C

Semiconductor integrated circuit device including a level shifter

A memory cell in the SRAM has three storing/holding states, i.e., a state where two storage nodes store 0, 1, a state where the two storage nodes store 1, 0, and a state where the two storage nodes store 1, 1. Therefore, the number of memory cells can be reduced by one half compared to the conventional case in which two memory cells were required to store three types of data signals.

Semiconductor memory device storing ternary data signal

Backgate biases of MOS transistors for generating a bias voltage in a bias voltage generation circuit generating the bias voltages are set shallow and backgate biases of MOS transistors of delay circuits of a ring oscillator constituting a clock generation circuit are set shallow. Thereby, a voltage range and a frequency range of a voltage controlled generation circuit to implement a phase synchronizing loop are both extended.

Voltage controlled oscillation circuit

A bias potential generation circuit in a level conversion circuit sets a bias potential applied to the backgate of an N-channel MOS transistor for pull-down at a positive potential when an input signal is set at the &ldquo;L&rdquo; level and the first and second signals are set at the &ldquo;H&rdquo; and &ldquo;L&rdquo; levels respectively, to lower the threshold voltage of the N-channel MOS transistor. Therefore, even if an amplitude voltage of the input signal is lowered, the operating speed can be increased.

Level conversion circuit converting logic level of signal

When an up signal UP is inputted, a switch is turned on and thereby a capacitor is charged to raise a control voltage VC. Further, when a down signal DWN is inputted, a switch is turned on and a capacitor discharges to hold the down signal DWN in the capacitor. Then, when a switch is turned on by a transmission signal EXE, an electric charge is injected into the capacitor to lower the control voltage VC. Further, when a switch is turned on by a reset signal RST, the capacitor is charged by an amplifier to cancel the down signal DWN. As a result, a low jitter reproduction clock can be generated regardless of an operating frequency.

Recovery circuit generating low jitter reproduction clock

A semiconductor integrated circuit includes: a first MOS transistor having one source/drain electrode for receiving a power supply voltage and the other source/drain electrode connected to a virtual power supply line; a second MOS transistor having one source/drain electrode connected to the virtual power supply line and the other source/drain electrode connected to a backgate power supply line; and a third MOS transistor having one source/drain electrode connected to the virtual power supply line and the backgate electrode connected to the backgate power supply line. When the first and second transistors are turned on, a voltage of the backgate electrode is forwardly biased to the one source/drain electrode in the third MOS transistor, thereby improving the operation speed of an internal circuit including the third MOS transistors in an active period.

Growing community of inventors

Tokyo, Japan

Hiromi Notani