Sony Corporation

Hiromi Nobukata

Ichiro Fujiwara

Kenichi Satori

Ihachi Naiki

Yoshitaka Osaka

An integrated circuit includes a semiconductor-circuit layer; metal layers formed on the semiconductor-circuit layer, one of the metal layers being a metal layer in which an active shield is formed; and an antenna formed by patterning in at least one of the metal layers that are below the metal layer in which the active shield is formed. The semiconductor-circuit layer includes an encryption circuit configured to receive a drive voltage and to perform encryption arithmetic; a power-supply circuit configured to provide the drive voltage to the encryption circuit; and a circuit system configured to receive a power-supply voltage from an external power supply.

Integrated circuit and electronic apparatus

A cryptographic processing apparatus includes: at least one register configured to store data for operation; a first operation block configured to execute an operation in accordance with data stored in the register; a second operation block configured to execute a logic operation between one of a register-stored value and a key and an operation result of the first operation block; and a decode block configured to decode binary data in units of the predetermined number of bits to convert the binary data into decode data having the number of bits higher than the number of bits of the binary data.

Cryptographic processing apparatus

An embodiment of the invention provides a circuit for detecting a malfunction generation attack, including: at least one sensor circuit adapted to detect a radiation of a light; and a detection circuit for detecting an intermediate voltage between a voltage corresponding to a High level and a voltage corresponding to a Low level in accordance with an output from the at least one sensor circuit, and outputting a detection signal. At least one sensor circuit has an output node a level at which is changed in accordance with the radiation of the light, and outputs a signal corresponding to the level at the output node which is changed in accordance with the radiation of the light. The detection circuit outputs the detection signal when a level of the output signal from the at least one sensor circuit reaches a level previously set.

Circuit for detecting malfunction generation attack and integrated circuit using the same

Disclosed herein is an encryption processing apparatus including: a first register device; a second register device; a first flag operation device; a first operation device; a second operation device; a round operation device; a third and a fourth operation device; a second flag operation device; and a fifth operation device.

Encryption processing apparatus

A nonvolatile memory system includes a drive voltage generator to generate a drive voltage on the basis of a power supply voltage; a plurality of normal memory cells serving as a nonvolatile memory storing data by accumulating charge of a polarity according to the data to be stored in a floating gate at a level according to the drive voltage generated by the drive voltage generator, the data being written in or read from the nonvolatile memory; a minimum voltage detecting memory cell serving as a nonvolatile memory in which charge of a level to cause a read error when the power supply voltage is equal to or lower than a minimum voltage of predetermined operation guarantee is accumulated in a floating gate; and a controller to output a read result of the normal memory cells if no read error occurs in a reading operation in the minimum voltage detecting memory cell.

Nonvolatile memory system and method for controlling nonvolatile memory

A nonvolatile semiconductor memory apparatus suitable to logic incorporation, by which a charge injection efficiency is high and hot electrons (HE) can be effectively injected at a low voltage is provided. A memory transistor (M) comprises first and second source/drain regions (S, SSL, D, SBL) formed on a semiconductor substrate (SUB, W), a charge storage film (GD) having a charge storage faculty and a gate electrode (WL). Memory peripheral circuits (to) generate a first voltage (Vd) and a second voltage (Vg-Vwell), apply the first voltage (Vd) to the second source/drain region (D, SBL) by using potential (0V) of the first source/drain region (S, SSL) as reference, apply the second voltage (Vg-Vwell) to the gate electrode (WL), generate hot electrons (HE) by ionization collision on the second source/drain region (D, SBL) side, and inject the hot electrons (HE) to the charge storage film (GD) from the second source/drain region (D, SBL) side at the time of writing data.

Nonvolatile semiconductor memory apparatus and method of producing the same

A nonvolatile semiconductor memory apparatus suitable to logic incorporation, by which a charge injection efficiency is high and hot electrons (HE) can be effectively injected at a low voltage is provided. A memory transistor (M) comprises first and second source/drain regions (S, SSL, D, SBL) formed on a semiconductor substrate (SUB, W), a charge storage film (GD) having a charge storage faculty and a gate electrode (WL). Memory peripheral circuits (to) generate a first voltage (Vd) and a second voltage (Vg&#x2212;Vwell), apply the first voltage (Vd) to the second source/drain region (D, SBL) by using potential (0V) of the first source/drain region (S, SSL) as reference, apply the second voltage (Vg&#x2212;Vwell) to the gate electrode (WL), generate hot electrons (HE) by ionization collision on the second source/drain region (D, SBL) side, and inject the hot electrons (HE) to the charge storage film (GD) from the second source/drain region (D, SBL) side at the time of writing data.

Nonvolatile semiconductor memory device and method of producing the same

A data transferring method for a nonvolatile memory composed of a flash memory. The flash memory allows a gaplessly read process to be performed unless a transfer error takes place. The flash memory comprises a first shift register, a second shift register, and a switching circuit. The first shift register stores data of the first half area of one page for a data re-transfer process in the case that a transfer error takes place. The second shift register stores data of the second half area of one page for a data re-transfer process in the case that a transfer error takes place. The switching circuit switches between output data of a memory cell array and output data of the first and second shift registers. As a result, data can be transferred at the logically maximum speed. In addition, a transfer error is detected page by page. When a transfer error is detected, the data re-transfer process is performed using the shift registers. Thus, the throughput can be suppressed from deteriorating.

Record medium and data transferring method using nonvolatile memory

A non-volatile semiconductor memory capable of dealing with eight levels and a method of writing data therein, which can shorten the writing time and perform verify read and normal read operations at a high speed by connecting a bit line to a supply source of a voltage in accordance with latch data of a latch circuit after charging all bit lines at a power source voltage level before a write operation, and by performing the write operations in parallel.

Non-volatile semiconductor memory and programming method of the same

A nonvolatile semiconductor storage device is disclosed. The device has memory cells for storing data corresponding to threshold voltages that vary corresponding to the amount of electric charge stored in electric charge storing portions, the amount of electric charge varying corresponding to voltages supplied to word lines and bit lines, multi-value data of n bits (where n&gE;2) being written in parallel and page by page to the memory cells. The device comprises a write controlling means for supplying a voltage for word lines as a pulse signal to memory cells and controlling the pulse width of the effective voltage of word lines corresponding to a substantial write time period of data written to the memory cells.

Nonvolatile semiconductor storage device and data writing method thereof

In a non-volatile semiconductor memory device of a flash type for recording multivalue data into memory cells, a control is made such that a word line voltage is set in accordance with a distribution state of a threshold voltage at the time of verification of data after the writing, a precharge of a bit line is controlled in accordance with data latched in a latch circuit, whether a threshold value of the memory cell exceeds a voltage applied to word line or not is detected depending on whether a current sufficiently flows in the memory cell or not, a state of the latch circuit is specified by a detection output, and when data is sufficiently written, predetermined data is set into the latch circuit. At the time of reading, a control is made so that a word line voltage is set in accordance with the distribution state of the threshold voltage, the state of the latch circuit is specified depending on whether a current sufficiently flows in the memory cell or not, and the read data is set into the latch circuit. Thus, the number of elements constructing the latch circuit is reduced.

Non-volatile semiconductor memory and method of verifying after writing

A nonvolatile semiconductor memory device having a memory cell in which an amount of charge stored in a charge storage unit changes according to a voltage supplied to a word line and a bit line, a threshold voltage changes according to that change, and data of a value according to the threshold voltage is stored, and writing trinary or more multi-bit data into memory cells in units of pages, provided with a precharging means for precharging all bit lines to a predetermined voltage before the write operation and a write control circuit having a latch circuit by which the write data is latched, making the bit line selected in accordance with an address discharge in accordance with the latch data, and performing write operations in parallel.

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Kanagawa, Japan

Hiromi Nobukata