Hitachi, Ltd.

Hiromi Nagayama

Shiro Baba

Naoki Mitsuishi

Tsutomu Hayashi

Yukihide Hayakawa

Expansion registers E0 to E7 are added to the existing general registers R0 to R7 built on-chip in a CPU 1 of 8 bits so that all the registers including the added expansion registers may be grasped in its entirety as address data to access to a memory or the like. The address operation is executed at a unit including both the expansion register and the corresponding general register. All the registers including the expansion registers are grasped as one unit of address data to handle the carry or borrow caused in the address operation. Since the expansion registers have their applications limited to the generation of address, the number of kinds or combinations of executable instructions is reduced without inviting a serious reduction in the data processing ability thereby to suppress the increase in the logical and physical scales of the CPU. The register is given 32 bits in its entirety by adding the expansion register Ei of 16 bits to the general registers RiH and RiL of 16 bits of the 8-bit CPU. This register can be used in its entirety, dividing it in half or by dividing it in quarters. As a result, the register can be excellently used on a software or hardware to reduce the logical and physical scales of the CPU. In respect of the latch of the address data using the register wholly or partially, moreover, the address space to be linearly used can be easily expanded.

Single-chip microcomputer having an expandable address area

Expansion registers E0 to E7 are added to the existing general registers R0 to R7 built on-chip in an 8-bit CPU (1) so that all the registers including the added expansion registers may be grasped in its entirety as address data to access to a memory or the like. The address operation is executed at a unit including both the expansion register and the corresponding general register. All the registers including the expansion registers are grasped as one unit of address data to handle the carry or borrow caused in the address operation. Since the expansion registers have their applications limited to the generation of address, the number of kinds or combinations of executable instructions is reduced without inviting a serious reduction in the data processing ability thereby to suppress the increase in the logical and physical scales of the CPU. The register is given 32 bits in its entirety by adding the expansion register Ei of 16 bits to the general registers RiH and RiL of 16 bits of the 8-bit CPU. This register can be used in its entirety, by dividing it in half or by dividing it in quarters. As a result, the register can be used on software or hardware to reduce the logical and physical scales of the CPU. In respect of the latch of the address data using the register wholly or partially, moreover, the address space to be linearly used can be easily expanded.

A CPU has an upper compatibility with a low-order CPU to expand a continuously usable address space relatively. For latching data information, registers are constructed for being an address register with a bit number larger than the address bit number of a low-order CPU. The data information has its byte/word size specified by the size bit of an operation code. The utilization of the data information of a long word size is specified by either the prefix code or the operation code to which is newly added the same bit number as that of the low-order CPU. For the data information of the byte size, the high-/low-orders of the byte size register to be utilized are specified by predetermined 1 bit of a register specifying field. For the data information of the word size, the high-/low-orders of the word size register are specified by the predetermined 1 bit of that data information.

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Kodaira, Japan

Hiromi Nagayama