Hitachi, Ltd.

Hitachi Vlsi Engineering Corp.

Texas Instruments Corporation

Hitachi Microcomputer Engineering, Ltd.

Hiromi Matsuura

Masaya Muranaka

Yasushi Takahashi

Kazuyuki Miyazawa

Masamichi Ishihara

Hidetoshi Iwai

Hiroyuki Uchiyama

Ryoichi Hori

Hisashi Nakamura

Yoshihisa Koyama

Satoshi Oguchi

Hidetomo Aoyagi

Shigetoshi Sakomura

Haruo Ii

Takeshi Kizaki

Toshiyuki Sakuta

Toshitugu Takekuma

Katsutaka Kimura

Yoshinobu Nakagome

Shunichi Sukegawa

Toshio Sasaki

Kazuyoshi Oshima

Hitoshi Tanaka

Yukihide Suzuki

Yasuhiro Kasama

Eiji Miyamoto

Kanehide Kenmizaki

Toshio Maeda

Osamu Sakai

Masanori Tazunoki

Eiji Yamasaki

Yasunori Orito

Osamu Okayama

Toshitugu Takemuma

Shiyuzo Shiozaki

A semiconductor memory device is provided which includes a substrate arrangement which is suitable for forming a large number of types of DRAMs having different package specifications, different bit structure and different operating modes. In conjunction with this, the bonding pads are arranged at optimum locations for accommodating the different package types. Various layout arrangements are also provided to minimize space and to improve access time. Additional features are provided, including improved output buffer circuitry, protection circuitry and testing methods to facilitate operation of the semiconductor memory device.

Semiconductor memory device with improved substrate arrangement to

A memory array is logically and/or physically divided into a plurality of blocks to allow test by individual blocks. When a plurality of column address strobe signals are provided and memory accessing is made by a plurality of bits to the memory array corresponding to the column address strobe signal, tests are independently conducted for each memory array by using the column address strobe signal.

Address multiplex semiconductor memory device for enabling testing of

A semiconductor device test circuit for inclusion on a semiconductor chip having a semiconductor device thereon, wherein a test mode with respect to the semiconductor device is not entered during normal use of the semiconductor device and the test mode can be entered without applying a voltage higher than the power supply voltage to an external terminal of the semiconductor device. The test circuit includes a decoder circuit which detects the matching of a first address input corresponding to a test mode, and a latch circuit which latches the signal indicating the matching of the first address input with a test mode. A second decoder circuit then detects the matching of a second address to the test mode, the second address being input when the matching signal for the first address has been latched. A second latch circuit latches the signal indicating the matching of the second address. A third address input is processed by a third decoder circuit and a third latch circuit in the same way. This means that when a plurality of addresses (three addresses in the described example) which are consecutively input to the respective decoder circuits are in a predetermined, specific combination, a test enable signal is output and the test mode is activated.

Semiconductor device test circuit having test enable circuitry and test

Each of a plurality of memory arrays is divided into a plurality of memory mats MAT00L-MAT07L to MAT10R-MAT17R in directions in which word lines and bit lines extend. First common data lines, that is, sub-IO lines, are provided which correspond to these memory mats and which are disposed in parallel to the word lines. Bit lines designating the corresponding memory mats are selectively connected to the first common data lines. Second common data lines, that is, main IO line groups MIOG0-MIOG7, are also provided and are disposed in parallel to the bit lines. Designated sub-IO lines are selectively connected to the second common data lines. Moreover, a plurality of main amplifiers forming a main amplifier unit MAU0 are orderly arranged in the direction in which the bit lines extend. These include a first main amplifier comprising a static current mirror amplifier which requires a relatively large operating current and a second main amplifier comprising a dynamic CMOS latch amplifier which requires only a relatively small operating current. These main amplifiers are put to proper use in conformity with the operating mode involved. By virtue of these arrangements, the number of parallel bits in a multibit parallel test mode of a dynamic RAM becomes expandable without being restricted by the number of the sub-IO lines correspondingly provided for each memory mat.

Semiconductor memory

A semiconductor integrated circuit memory structure is provided which uses macro-cellulated circuit blocks that can permit a very large storage capability (for example, on the order of 64 Mbits in a DRAM) on a single chip. To achieve, this, a plurality of macro-cellulated memory blocks can be provided, with each of the memory blocks including a memory array as well as additional circuitry such as address selection circuits and input/output circuits. Other peripheral circuits are provided on the chip which are common to the plurality of macro-cell memory blocks. The macro-cell memory blocks themselves can be formed in an array so that their combined storage capacity will form the large overall storage capacity of the chip. The combination of the macro-cell memory blocks and the common peripheral circuitry for controlling the memory blocks permits a faster and more efficient refreshing operation for a DRAM. This is enhanced by a LOC (Lead On Chip) arrangement used in conjunction with the memory blocks.

Semiconductor integrated circuit device having a plurality of memory

A semiconductor integrated circuit device is provided which includes a memory cell array located in a generally central area of a semiconductor substrate with peripheral circuits located at both ends of the semiconductor substrate. A wiring layer is also provided which couples the peripheral circuits to one another. This wiring layer is arranged to have a double-layer structure of first and second aluminum layers which are electrically coupled to one another.

Semiconductor integrated circuit device

A semiconductor memory having a memory array, a first and a second selection line which are connected to a memory cell, and a selection means which selects either one of the selection lines. The selection means includes a selection circuit which optionally selects the first selection line or the second selection line when an address signal corresponding to the first selection line is aligned with a predetermined address signal.

Semiconductor memorizing device

In a dynamic RAM having a memory array of a folded bit line arrangement, the memory array has a plurality of bit line pairs. A plurality of word lines and dummy word lines cross each of the bit line pairs so as to apply coupling noises of the same phase to the bit lines constituting each of the bit line pairs. The levels of the coupling noises applied to the bit lines constituting each of the bit line pairs, however, are also affected by the stray capacitance between the bit lines. Since the bit line disposed at an end part of the memory array has only one adjacent bit line disposed on one side thereof, only a relatively small stray capacitance is connected to the bit line. This causes the coupling noise between bit lines at the bit line disposed at an end part of the memory array to be different than the degree of coupling noise between other bit lines in the array. To overcome the unbalance this causes, an additional dummy bit line is disposed at an end part of the memory array in order to increase the stray capacitance connected to the bit line disposed at the end part of the memory array. Consequently, common mode noises at levels substantially equal to each other are applied to all the bit line pairs. A differential type sense amplifier connected to each of the bit line pairs does not respond to the common mode noise. Accordingly, the minute data signal set by a selected memory cell and a dummy memory cell in reading out data is amplified with substantially no deleterious effect being caused by noise.

Dynamic RAM integrated circuit device

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Tokorozawa, Japan

Hiromi Matsuura