Renesas Technology Corp.

Renesas Electronics Corporation

Hitachi, Ltd.

Other

Hitachi Ulsi Systems Co., Ltd.

Hitachi Ulsi Engineering Corp.

Hitachi Microcomputer System, Ltd.

Hiromi Abe

Masayuki Suzuki

Naotaka Hashimoto

Shinichi Fukada

Hiroshi Momiji

Shinji Nishihara

Masanori Kojima

Shuji Ikeda

Hiroyuki Uchiyama

Masanao Sato

Masashi Sahara

Toshihiko Akiba

Bunji Yasumura

Shinichi Ishida

Hideaki Tsugane

Yoshiaki Yoshiura

Sonoko Tohda

Hideo Miura

Atushi Ogishima

Sonoko Abe

Hiromi Todorobaru

Masayuki A Suzuki

Akira Nagai

Masaharu Kubo

Kenichi Yamamoto

Ichiro Anjo

Hitoshi Akamine

Akira Yajima

Osamu Kubo

Provided is a semiconductor device having a pad on a semiconductor chip, a first passivation film formed over the semiconductor chip and having an opening portion on the pad of a probe region and a coupling region, a second passivation film formed over the pad and the first passivation film and having an opening portion on the pad of the coupling region, and a rewiring layer formed over the coupling region and the second passivation film and electrically coupled to the pad. The pad of the probe region placed on the periphery side of the semiconductor chip relative to the coupling region has a probe mark and the rewiring layer extends from the coupling region to the center side of the semiconductor chip. The present invention provides a technology capable of achieving size reduction, particularly pitch narrowing, of a semiconductor device.

Method of manufacturing semiconductor device

Manufacturing method of semiconductor device

Semiconductor device with bond pad wiring lead-out arrangement avoiding bond pad probe mark area

Semiconductor device

Semiconductor device and manufacturing method of the same

A Co silicide layer having a low resistance and a small junction leakage current is formed on the surface of the gate electrode, source and drain of MOSFETS by silicidizing a Co film deposited on a main plane of a wafer by sputtering using a high purity Co target having a Co purity of at least 99.99% and Fe and Ni contents of not greater than 10 ppm, preferably having a Co purity of 99.999%.

Method of fabricating semiconductor integrated circuit device

An implantation step of a dopant ion for forming source and drain regions (S and D) is divided into one implantation of a dopant ion for forming a p/n junction with a well region (), and one implantation of a dopant ion that does not influence a position of the p/n junction between the source and drain regions (S and D) and the well region with a shallow implantation depth and' a large implantation amount. After conducting an activation heat treatment of the dopant, a surface of the source/drain region is made into cobalt suicide, so that the source/drain region (S and D) can have a low resistance, and a p/n junction leakage can be reduced.

Method of fabricating semiconductor device

An implantation step of a dopant ion for forming source and drain regions (S and D) is divided into one implantation of a dopant ion for forming a p/n junction with a well region (), and one implantation of a dopant ion that does not influence a position of the p/n junction between the source and drain regions (S and D) and the well region with a shallow implantation depth and a large implantation amount. After conducting an activation heat treatment of the dopant, a surface of the source/drain region is made into cobalt silicide, so that the source/drain region (S and D) can have a low resistance, and a p/n junction leakage can be reduced.

Method for fabricating semiconductor device

Method of fabricating semiconductor integrated circuit device with 99.99 wt% cobalt

A Co silicide layer having a low resistance and a small junction leakage current is formed on the surface of the gate electrode, source and drain of MOSFETs by silicidizing a Co film deposited on a main plane of a wafer by sputtering using a high purity Co target having a Co purity of at least 99.99% and Fe and Ni contents of not greater than 10 ppm, preferably having a Co purity of 99.999%.

An implantation step of a dopant ion for forming source and drain regions (S and D) is divided into one implantation of a dopant ion for forming a p/n junction with a well region (), and one implantation of a dopant ion that does not influence a position of the p/n junction between the source and drain regions (S and D) and the well region with a shallow implantation depth and' a large implantation amount. After conducting an activation heat treatment of the dopant, a surface of the source/drain region is made into cobalt silicide, so that the source/drain region (S and D) can have a low resistance, and a p/n junction leakage can be reduced.

Growing community of inventors

Tokyo, Japan

Hiromi Abe