Kabushiki Kaisha Toshiba

Kioxia Corporation

Toshiba Memory Corporation

Hirokuni Yano

Toshikatsu Hida

Shinichi Kanno

Kazuya Kitsunai

Seiji Maeda

Junji Yano

Shigehiro Asano

Tatsunori Kanai

Hidenori Matsuzaki

Hiroshi Yao

Kenichiro Yoshii

Osamu Torii

Toshiki Kizu

Mitsunori Tadokoro

Shinji Yonezawa

Takuya Hayashi

Kiyoko Sato

Nobuo Sakiyama

Takashi Hirao

Tatsuya Sumiyoshi

Hajime Yamazaki

Toshio Shirakihara

Hisako Tanaka

Hiroki Matsudaira

Takeshi Yokokawa

Yoshimi Niisato

Hironobu Miyamoto

Kenji Tanaka

Ryoichi Kato

Ryuji Nishikubo

Nobuhiro Ono

Hirokazu Morita

Akira Sawaoka

Aurelien Nam Phong Tran

Yasunori Nakamura

Eiji Yoshihashi

Shoji Ninoi

Takahiro Totsuka

Hida Toshikatsu

Naoki Otsuka

Naoki Ootsuka

Seiji Norimatsu

A memory system includes a nonvolatile memory including a plurality of blocks as data erase units, a measuring unit which measures an erase time at which data of each block is erased, and a block controller which writes data supplied from at least an exterior into a first block which is set in a free state and whose erase time is oldest.

Memory system and control method thereof

A semiconductor storage device includes a first memory area configured in a volatile semiconductor memory, second and third memory areas configured in a nonvolatile semiconductor memory, and a controller which executes following processing. The controller executes a first processing for storing a plurality of data by the first unit in the first memory area, a second processing for storing data outputted from the first memory area by a first management unit in the second memory area, and a third processing for storing data outputted from the first memory area by a second management unit in the third memory area.

Semiconductor storage device with volatile and nonvolatile memories to allocate blocks to a memory and release allocated blocks

A storage device includes a hardware random number generator configured to generate a random number; a first memory; and a controller configured to control the hardware random number generator and the first memory. The controller is configured to: obtain the random number generated by the hardware random number generator after the storage device is powered up; obtain a first trace log of the storage device; and store, into the first memory, a log resulting from appending the obtained random number to the first trace log, as a second trace log.

Storage device and method of controlling storage device

A memory system of one embodiment includes: a nonvolatile memory including a plurality of word lines each connected to memory cells, each one of the memory cells being capable storing two bits, the memory cells connected to one of the plurality of word lines constituting an upper page and a lower page, each one of the pages being a unit of data programming; a random access memory configured to store an address translation table indicating relationships between logical addresses designated by a host and physical addresses in the nonvolatile memory. The memory system of the embodiment further includes a memory controller which execute data fixing for saving the address translation table from the random access memory to the nonvolatile memory; and write dummy data to at least one page subsequent to the page in which valid data has been written in the nonvolatile memory before executing the data fixing.

Memory system and method for writing data into memory system

A memory system in embodiments includes a nonvolatile semiconductor memory that stores user data, a forward lookup address translation table and a reverse lookup address translation table, and a controller. The controller is configured to determine that the user data stored in the nonvolatile semiconductor memory is valid or invalid based on these two tables. The controller may perform data organizing of selecting data determined valid and rewriting the data in a new block. The controller may perform write processing and rewriting processing to the new block alternately at a predetermined ratio. The controller may determine whether a predetermined condition is satisfied on a basis of addresses included in write requests and write data in the MLC mode when the condition is satisfied and write data in the SLC mode when the condition is not satisfied.

Memory system and control method of memory system

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Tokyo, Japan

Hirokuni Yano