Matsushita Electric Industrial Co., Ltd.

Panasonic Corporation

Panasonic Intellectual Property Management Co., Ltd.

Hirokuni Fujiyama

Takashi Morie

Akira Yamamoto

Shiro Dosho

Hiroyuki Nakahira

Hiroki Mouri

Hiroya Ueno

Kouji Okamoto

Ichiro Yamane

Akinori Matsumoto

Joji Hayashi

Katsumasa Hijikata

Shinji Miyamoto

A voltage detection circuit includes a reference voltage and current supply configured to generate a reference voltage and a reference current; a switching element configured to shift from an off-state to an on-state when the reference voltage is higher than a predetermined threshold voltage; a current mirror circuit allowing a current corresponding to the reference current to flow through the switching element in the on-state; a capacitive element coupled in series to the current mirror circuit and charged with the current flowing through the switching element; and an inverter configured to output an enable signal activated based on a terminal voltage of the capacitive element.

Voltage detection circuit

A first resistance element is coupled between a first rectifying element and an output node at which a reference voltage is generated. Second and third resistance elements are coupled in series between a second rectifying element and the output node. A differential amplifier outputs a control voltage corresponding to a difference between a first voltage generated at a connection point of the first rectifying element and the first resistance element and a second voltage generated at a connection point of the second resistance element and the third resistance element. A control circuit supplies a control current corresponding to the control voltage from the differential amplifier. A start-up circuit causes, by supplying a start-up current to the output node in response to supply of a power supply voltage, transition from a first stable state to a second stable state.

Reference voltage generation circuit with start-up circuit

There is provided a filter characteristic adjusting apparatus and a filter characteristic adjusting method which can avoid an increase in circuit scale of the filter characteristic adjusting apparatus, and can speedily adjust a characteristic frequency of the filter to a desired frequency. When performing characteristic adjustment for the filter, the test signal generation unit () generates a test signal (s) which is a pulse signal having the same frequency as the characteristic frequency of the filter () on the basis of a reference signal (s), and a phase-shifted test signal (s') that is obtained by shifting the phase of the test signal (s) by a predetermined amount with a phase shift unit () in a control signal generation unit () is compared with a filter output signal (s) that is obtained by inputting the test signal (s) into the filter () to obtain a phase difference between the signals, and then the phase difference is subjected to a binary search to generate a control signal (s).

Filter characteristic adjusting apparatus and filter characteristic adjusting method

A pseudo-image signal producing section produces a pseudo-image signal imitating an actual image signal. An amplitude detection section detects the amplitude of the pseudo-image signal having passed through a complex filter circuit. A filter control section controls an element value control section in the complex filter circuit so as to decrease the detected amplitude. The element value control section performs an element value adjustment so that absolute element values of a pair of elements corresponding to each other in two filter circuits in the complex filter circuit increase/decrease in opposite directions.

Complex filter circuit and receiver circuit

A write compensation circuit of a recording device includes a first delay portion driven by a first driving voltage, for receiving a clock signal, delaying the clock signal by a first delay time, and outputting the delayed clock signal, and a voltage supplying portion for supplying the first driving voltage to the first delay portion in such a manner that the first delay time is substantially equal to a clock period of the clock signal.

Write compensation circuit and signal interpolation circuit of recording device

In a filter adjustment circuit for an analog filter circuit such as a Gm-C filter, an input signal IS from a reference signal generation circuitis inputted to a Gm-C filterto be filtered and then converted by a conversion circuitto a digital signal. A reference signal RS from the reference signal generation circuitis converted by a conversion circuitto a digital signal. The two converted signals are held in time series in a holding circuit. A timing generation circuitgenerates an update timing signal en based on a reference time-series signal ref from the holding circuitA control signal generation circuitgenerates a control signal CS based on the reference time-series signal ref and a filter output time-series signal tgt, each from the holding circuit. The control signal CS is inputted to the Gm-C filterin response to the update timing signal en to adjust the gain of the Gm-C filter. As a result, variations in the response characteristics of the Gm-C filterare adjusted with high accuracy with a simple circuit structure.

Filter adjustment circuit

In an offset control circuit, a voltage/current converting portion generates differential current (I+ and I&#x2212;) that are proportional to a potential difference between differential input voltage signals (VIN+ and VIN&#x2212;), and an offset adjusting current-generating portion generates offset adjusting currents (Iofs+ and Iofs&#x2212;). In a current/voltage converting portion, a current (Ir) that is proportional to a potential difference between differential terminals flows through. Differential current output terminals, offset adjusting current-output terminals and the differential terminals are connected. The offset components contained in the differential input voltage signals (VIN+ and VIN&#x2212;) are adjusted with the offset adjusting currents (Iofs+ and Iofs&#x2212;), and differential output voltage signals (VO+ and VO&#x2212;) in which the offset components are added to the differential input voltage signals (VIN+ and VIN&#x2212;) are generated.

Offset control circuit

In a signal reproduction block of a DVD reproduction apparatus, an output signal line for outputting a characteristic information signal representing a characteristic of a filter incorporated in the signal reproduction block to the outside is additionally provided on the output side of an A/D converter. In this way, it is possible to prevent an analog data signal from deteriorating during a data signal reproduction process due to a parasitic effect of the output signal line. Moreover, the filter characteristic information signal is output through the output signal line after it is convened to a digital signal by the A/D convener, thereby avoiding the deterioration the characteristic information signal and thus improving the measurement precision.

Signal reproduction block

An adaptive digital filter of the present invention includes: a pipelined filtering section for performing a filtering operation based on input data and coefficient data so as to output filtered data; and a non-pipelined adaptation section for outputting the coefficient data to the pipelined filtering section by performing a coefficient adaptation operation in a non-pipelined process based on the input data and the filtered data so that the filtered data output from the pipelined filtering section converges to a predetermined reference value.

Adaptive digital filter

The variable gain amplifier of the invention includes an input node pair, a first output node pair, a voltage-current converter, a plurality of first resistances, a first current source, a second current source, a second output node pair, a third output node pair and a switch circuit. A differential signal supplied to the input node pair is amplified with a predetermined gain (first gain) and output from the second output node pair. The differential signal is also amplified with a gain (second gain) corresponding to the resistance value between one interconnection node and another interconnection node, among the interconnection nodes connecting the plurality of first resistances, connected to the third output node pair via the switch circuit, and output from the third output node pair. The second gain can be changed by changing the two interconnection nodes connected to the third output node pair via the switch circuit.

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Hyogo, Japan

Hirokuni Fujiyama