Panasonic Liquid Crystal Display Co., Ltd.

Japan Display Inc.

Hitachi Displays, Ltd.

Canon Kabushiki Kaisha

Panasonic Intellectual Property Corporation of America

Hiroko Sehata

Toshiki Kaneko

Hideo Tanabe

Atsushi Hasegawa

Masaru Takabatake

Takahiro Ochiai

Mitsuru Goto

Hiroyuki Higashijima

Yoshihiro Kotani

Kouichi Kotera

Kenichi Akiyama

Hajime Akimoto

Shuuichirou Matsumoto

Gou Yamamoto

A shift register circuit, including: a plurality of clock signal lines each supplying a clock pulse respectively; a plurality of cascade-connected register circuits including a top register circuit, and main register circuits providing between the top register circuit and the bottom register circuit; and a forward scan signal line supplying a forward scan signal to the plurality of cascade-connected register circuits.

Shift register circuit

A LCD device having a large pixel holding capacitance includes opposedly facing first and second substrates, and liquid crystal between them. The first substrate includes a video signal line, a pixel electrode, a thin film transistor having a first electrode connected to the video signal line and a second electrode connected to the pixel electrode, a first silicon nitride film formed above the second electrode, an organic insulation film above the first silicon nitride film, a capacitance electrode above the organic insulation film, and a second silicon nitride film above the capacitance electrode and below the pixel electrode. A contact hole etched in both the first and second silicon nitride films connects the second electrode and the pixel electrode to each other. A holding capacitance is formed by the pixel electrode, the second silicon nitride film and the capacitance electrode.

Manufacturing method for liquid crystal display device

A display device including a bidirectional shift register circuit, including: a plurality of cascade-connected register circuits; various circuits for setting various nodes to various voltage levels responsive to various signals input to various terminals; and an output circuit which outputs the clock pulse as an output pulse when the voltage of the first node is high level, wherein, at the forward shift operation, the bottom dummy register circuit is not input the reset signal and the first node of the bottom dummy register circuit is reset if the initial reset circuit of the bottom dummy register circuit receives the backward trigger signal, and wherein, at the backward shift operation, the top dummy register circuit is not input the reset signal and the first node of the top dummy register circuit is reset if the initial reset circuit of the top dummy register circuit receives the forward trigger signal.

Bidirectional shift register circuit

A plurality of cascade-connected register circuits which comprises a bidirectional shift register include a top register circuit, a bottom register circuit, and main register circuits. The register circuit has an output circuit which outputs one of four-phase clock pulses when a voltage of a first node is an active level; a second output circuit which outputs a non-active level when a voltage of a second node is the active level; a second node reset circuit which sets the second node to the non-active level when a voltage of a second node reset terminal is the active level. The forward scan signal sets the voltage of the first node of the top register circuit to the active level, and the forward scan signal sets the voltage of the second node reset terminal of the bottom register circuit to the active level.

Bidirectional shift register and image display device using the same

Growing community of inventors

Sapporo, Japan

Hiroko Sehata