Fujitsu Corporation

Hiroko Douchi

Naoharu Shinozaki

Yoshihiro Takemae

Masao Taguchi

Hiroyoshi Tomita

Yasurou Matsuzaki

Masao Nakano

Yoshinori Okajima

Koichi Nishimura

Yasuharu Sato

Kenichi Kawasaki

Terumasa Kitahara

Toshiya Uchida

Kazuhiro Nunomiya

Disclosed is a semiconductor device for outputting an output signal with a given phase held relative to an external clock despite a difference in characteristic, a change in temperature, and a fluctuation in supply voltage. The semiconductor device comprises an input circuit for inputting the external clock and outputting a reference signal, an output circuit for receiving an output timing signal and outputting an output signal according to the timing of the output timing signal, and an output timing control circuit for controlling the output timing so that the output signal exhibits a given phase relative to the external clock. The output timing control circuit includes a delay circuit for delaying the reference signal by a specified magnitude and generating an output timing signal, a phase comparison circuit for comparing the phase of the output timing signal with the phase of the reference signal, and a delay control circuit for specifying the magnitude of a delay to be produced by the delay circuit according to the result of comparison performed by the phase comparison circuit.

Input/output data synchronizing device

A clock signal generator which is particularly useful for a double data rate SDRAM (DDR-SDRAM) includes two or more clock signal input buffers and an enable signal input buffer. The clock signal generator generates internal clock signals that fluctuate at substantially different timings, yet the relationship between the internal clock signals with respect to validation and invalidation timing is constant. A latch circuit latches an enable signal from the enable signal buffer in accordance with a first internal clock signal from a first one of the clock signal buffers. A first enable signal connected to the latch circuit holds the latched enable signal in accordance with the first internal clock signal. A second enable circuit receives the first enable signal and the first internal clock signal and generates a second enable signal used to activate the clock signal buffers. A logic gate receives the first enable signal and the first internal clock signal and controls the output of the first internal clock signal.

Clock signal generator for generating signal with differing phase for an integrated circuit

Semiconductor device, semiconductor system, and digital delay circuit

Clock signal generator for an integrated circuit

A load adjusting circuit 36 adjusts the load value L=L2 of a dummy load circuit 31x corresponding to the outputs of a frequency determining circuit 37 and an interface determining circuit 35 as L2=L1-.DELTA.L holding, where L=L1 is a proper value in the case that the access time does not depend on the frequency of the data DQ and .DELTA.L corresponds to a half of the maximum value tlc of the deviation of the access time that varies corresponding to the frequency of the data DQ. A DLL circuit 40 delays a internal clock iCLK by a time .delta.tx so that a difference between phases of the clock iCLK and a dummy internal clock d.sub.-- iCLK becomes a predetermined value. The delay time .delta.tx is equal to a value determined in such a way that .delta.tx=67 tx0 is determined with activating the DLL circuit 40, tlc is determined and .delta.tx is finally determined as .delta.tx=.delta.tx0+ tlc/2 or .delta.tx=.delta.tx0-tlc/2 due to the condition of data frequency at determining .delta.tx0.

Hold time margin increased semiconductor device and access time

The present invention relates to a level interface circuit, which receives a first interface input signal having a level H and a level L, as fixed potentials, and a first reference level which is midway therebetween, and a second interface input signals having a level H, a level L and a second reference level determined in accordance with a power source voltage, and which compares an input signal of one of said first and second interface input with one of said first and second reference level signal and generates an output signal, said level interface circuit further comprising: a first and a second transistors, having a common source connection, for receiving said input signal and said reference level signal at respective gates; a current source transistor connected to said source of said first and said second transistors; a load circuit connected to drains of said first and said second transistors; a voltage control transistor provided between said load circuit and said power voltage source; and a voltage controller for determining whether said input signal corresponds to said first or said second interface input, and increasing or reducing an impedance of said power control transistor in accordance with the determination.

Level interface circuit

Growing community of inventors

Kawasaki, Japan

Hiroko Douchi