Fuji Electric Co., Ltd.

Fuji Electric Device Technology Co., Ltd.

Fuji Electric Systems Co. Ltd.

Octec, Inc.

Fuji Electric., Ltd.

Hiroki Wakimoto

Yuichi Onozawa

Masahito Otsuki

Takahiro Tamura

Tsunehiro Nakajima

Takashi Yoshimura

Hiroshi Takishita

Koh Yoshikawa

Masaaki Ogino

Seiji Momota

Takashi Hayashi

Koji Sasaki

Kenichi Kazama

Akio Shimizu

Kenichi Iguchi

Eri Ogawa

Shunsuke Tanaka

Haruo Nakazawa

Masayuki Miyazaki

Takashi Shiigi

Yasushi Miyasaka

Misaki Takahashi

Tomoyuki Yamazaki

Kazuo Shimoyama

Katsuya Okumura

Toru Muramatsu

Ryohei Takayanagi

A p-type semiconductor region is formed in a front surface side of an n-type semiconductor substrate. An n-type field stop (FS) region including protons as a donor is formed in a rear surface side of the semiconductor substrate. A concentration distribution of the donors in the FS region include first, second, third and fourth peaks in order from a front surface to the rear surface. Each of the peaks has a peak maximum point, and peak end points formed at both sides of the peak maximum point. The peak maximum points of the first and second peaks are higher than the peak maximum point of the third peak. The peak maximum point of the third peak is lower than the peak maximum point of the fourth peak.

Semiconductor device, and method of manufacturing semiconductor device

A semiconductor device comprises: an n-type semiconductor substrate; a p-type anode region formed in the semiconductor substrate on its front surface side; an n-type field stop region formed in the semiconductor substrate on its rear surface side with protons as a donor; and an n-type cathode region formed in the semiconductor substrate to be closer to its rear surface than the field stop region is, wherein a concentration distribution of the donor in the field stop region in its depth direction has a first peak, and a second peak that is closer to the rear surface of the semiconductor substrate than the first peak is, and has a concentration lower than that of the first peak, and a carrier lifetime in at least a partial region between the anode region and the cathode region is longer than carrier lifetimes in the anode region.

Manufacturing method for controlling carrier lifetimes in semiconductor substrates that includes injection and annealing

To prevent an intermediate region from contacting a cathode electrode even if a cathode region is partially defective. There is provided a semiconductor device with a semiconductor substrate that has a field stop region where first impurities of a first conduction type are implanted, an intermediate region that is formed on a back surface side of the field stop region and where second impurities of a second conduction type are implanted, and a cathode region of the first conduction type that is formed on a back surface side of the intermediate region. In a back surface of the semiconductor substrate, a concentration of the first impurities is higher than a concentration of the second impurities.

Semiconductor device and semiconductor device manufacturing method

An embodiment of a silicon carbide semiconductor device includes one or more inner cells each having a MOSFET and one or more outer peripheral cells that does not have a MOSFET structure, and the area (surface area) of the pcontact region of each of the outermost peripheral cells is less than the surface area of an pcontact region of each of the inner cells, for example, so that a unit total resistance of pcontact regions of the outermost peripheral cells, as measured in a depth direction of the semiconductor substrate with respect to a unit area in a surface of the semiconductor substrate, is greater than a unit total resistance of the pcontact regions of the inner cells, as measured in the depth direction of the semiconductor substrate with respect to the unit area in the surface of the semiconductor substrate.

Silicon carbide semiconductor device

To improve withstand capability of a semiconductor device during reverse recovery, provided is a semiconductor device including a semiconductor substrate having a first conduction type; a first region having a second conduction type that is formed in a front surface of the semiconductor substrate; a second region having a second conduction type that is formed adjacent to the first region in the front surface of the semiconductor substrate and has a higher concentration than the first region; a third region having a second conduction type that is formed adjacent to the second region in the front surface of the semiconductor substrate and has a higher concentration than the second region; an insulating film that covers a portion of the second region and the third region; and an electrode connected to the second region and the first region that are not covered by the insulating film.

Semiconductor device

Provided is a semiconductor device comprising: a first conductivity type base layer having a MOS gate structure formed on its front surface side; a second conductivity type first collector layer formed on a rear surface side of the base layer; a second conductivity type second collector layer formed on a rear surface side of the first collector layer with a material the same with that of the base layer, the second collector layer formed to be thinner than the first collector layer and having a higher impurity concentration than that of the first collector layer; a collector electrode formed on a rear surface side of the second collector layer; and a second conductivity type separation layer surrounding the MOS gate structure on a front surface side of the base layer and formed from a front surface of the base layer to a front surface of the first collector layer.

Semiconductor device and method of manufacturing semiconductor device

In a method for manufacturing a reverse blocking MOS semiconductor device, a gettering polysilicon layer is formed on a rear surface of an FZ silicon substrate. Then, a pisolation layer for obtaining a reverse voltage blocking capability is formed. A front surface structure including a MOS gate structure is formed on a front surface of the FZ silicon substrate. The rear surface of the FZ silicon substrate is ground to reduce the thickness of the FZ silicon substrate. The gettering polysilicon layer is formed with such a thickness that it remains, without being vanished by single crystallization, until a process for forming the front surface structure including the MOS gate structure ends. Therefore, it is possible to sufficiently maintain the gettering function of the gettering polysilicon layer even in a heat treatment process subsequent to an isolation diffusion process.

Method for manufacturing semiconductor device using a gettering layer

Some embodiments of the present invention relate to a semiconductor device and a method of manufacturing a semiconductor device capable of preventing the deterioration of electrical characteristics. A p-type collector region is provided on a surface layer of a backside surface of an n-type drift region. A p-type isolation layer for obtaining reverse blocking capability is provided at the end of an element. In addition, a concave portion is provided so as to extend from the backside surface of the n-type drift region to the p-type isolation layer. A p-type region is provided and is electrically connected to the p-type isolation layer. The p-type isolation layer is provided so as to include a cleavage plane having the boundary between the bottom and the side wall of the concave portion as one side.

Method of manufacturing semiconductor device

A method includes forming on a first main surface of a semiconductor wafer of a first conduction type, a gate electrode of a semiconductor element, an edge termination region for forming a breakdown voltage of the semiconductor element, and a first semiconductor region of a second conduction type which surrounds the semiconductor element and the edge termination region. A groove may be formed to reach the first semiconductor region from a second main surface of the semiconductor wafer. The groove is formed so that a portion of the semiconductor wafer, that forms an outer circumferential end of the semiconductor wafer, remains and the groove is further towards a center of the semiconductor wafer than the outer circumferential end. A third semiconductor region of the second conduction type is on a side wall of the groove and electrically connects the first semiconductor region and a second semiconductor region.

Method for manufacturing semiconductor device

A semiconductor device includes an active region in which current flows when the semiconductor device is in an on state and a breakdown voltage structure portion which surrounds the active region. In the active region, a MOS gate structure includes, a p well region, an nsource region, a gate electrode, and a source electrode is provided on the front surface of a semiconductor substrate. A drain electrode which comes into contact with an ndrift region is provided from the rear surface to the side surface of the semiconductor substrate. The drain electrode forms a Schottky contact with the ndrift region which is the semiconductor substrate. In the breakdown voltage structure portion, a leakage current reducing layer reduces leakage current from the outer circumferential edge of the semiconductor substrate and is provided at least at the outer circumferential edge of the semiconductor substrate.

A semiconductor device, including a silicon substrate having a first major surface and a second major surface, a front surface device structure formed in a region of the first major surface, and a rear electrode formed in a region of the second major surface. The rear electrode includes, as a first layer thereof, an aluminum silicon film that is formed by evaporating or sputtering aluminum-silicon onto the second major surface, the aluminum silicon film having a silicon concentration of at least 2 percent by weight and a thickness of less than 0.3 &#x3bc;m.

Semiconductor device with an electrode including an aluminum-silicon film

A semiconductor device is disclosed which includes active section, edge termination sectionhaving a voltage blocking structure and disposed around active section, and separation sectionhaving a device separation structure and disposed around edge termination section. A surface device structure is formed on the first major surface of active section, trenchis formed in separation sectionfrom the second major surface side, and p-type separation regionis formed on the side wall of trenchsuch that p-type separation regionis in contact with p-type channel stopper regionformed in the surface portion on the first major surface side and p-type collector layerformed in the surface portion on the second major surface side. The semiconductor device and the method for manufacturing the semiconductor device according to the invention facilitate preventing the reverse blocking voltage from decreasing and shorten the manufacturing time of the semiconductor device.

Growing community of inventors

Matsumoto, Japan

Hiroki Wakimoto