Omnivision Technologies, Inc.

Hiroki Ui

Hiroaki Ebihara

Tiejun Dai

Rui Wang

Sang Joo Lee

Takatoshi Nakata

Eiichi Funatsu

Nobuhiro Yanagisawa

Naoki Kitazawa

Ryuichi Moriizumi

A pixel circuit, including a pixel array comprising a plurality of pixels, a plurality of analog to digital converters (ADCs), where during a pixel data readout the plurality of ADCs is communicatively coupled to a respective pixel of the plurality of pixels to receive image data from the respective pixel of the plurality of pixels, a plurality of judge blocks, wherein each judge block is communicatively coupled to a respective ADC of the plurality of ADCs and wherein each judge block is configured to select and transmit gain data based on comparing an output of the respective ADC to a predetermined threshold for the respective ADC, and an image signal processor (ISP) configured to receive outputs from the plurality of ADCs, and combine the outputs of the plurality of ADCs to produce a combined converted value for the respective pixel.

Adaptive data selection for DCG / DAG

An image sensor comprises a plurality of high sensitivity photoelectric conversion elements, a plurality of low sensitivity photoelectric conversion elements, and a processor for processing signals read out from the plurality of low sensitivity photoelectric conversion elements and the plurality of high sensitivity photoelectric conversion elements, where the processor is configured to read out signals from the plurality of low-sensitivity photoelectric conversion elements multiple times in a single frame after multiple exposures and obtain a plurality of images of low-sensitivity in the single frame at different times.

Image sensors having image blur correction

An image sensor includes a plurality of pixels that is arranged in a matrix and each of which outputs a signal in response to incident light, wherein readout of data can be performed with respect to the plurality of pixels, and simultaneous readout of data of a plurality of columns of pixels can be performed, and at least one pixel of the plurality of columns of pixels to be read simultaneously can be read for phase detection with respect to each of divided sub-pixels. The image sensor is configured to, with n rows as a readout unit where n is an integer of 2 or more, perform readout for at least one sub-pixel of at least one pixel in one readout cycle within the readout unit, perform readout for each pixel including phase detection readout for the other sub-pixel of the at least one pixel in which the at least one sub-pixel has been read in the one readout cycle, in another readout cycle within the readout unit, and end the readout for the readout unit with the n+1 readout cycles.

Image sensor and method for reading out signal of image sensor

A pixel array includes pixel cells, each including photodiodes. A source follower is coupled to generate an image signal in response image charge generated by the photodiodes. A first row select transistor is coupled to the source follower to output the image signal of the pixel cell. Pixel cells are organized into columns including a first column and a second column. The first row select transistors of the pixel cells of the first and second columns of pixel cells are coupled to first and second column bitlines, respectively. The pixel cells of the second column of pixel cells further include a second row select transistor coupled to the source follower to output the respective image signal to the first column bitline.

Dual row select pixel for fast pixel binning

A pixel array includes pixel cells disposed in semiconductor material. Each of the pixel cells includes photodiodes, and a floating diffusion to receive image charge from the photodiodes. A source follower is coupled to the floating diffusion to generate an image signal in response image charge from the photodiodes. Drain regions of first and second row select transistors are coupled to a source of the source follower. A common junction is disposed in the semiconductor material between gates of the first and second row select transistors such that the drains of the first and second row select transistors are shared and coupled together through the semiconductor material of the common junction. The pixel cells are organized into a rows and columns with bitlines.

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Yokohama, Japan

Hiroki Ui