Renesas Technology Corp.

Hitachi Ulsi Systems Co., Ltd.

Other

Hiroki Ueno

Takashi Akioka

Kinya Mitsumoto

Masao Shinozaki

Akihisa Aoyama

Parasitic capacitances formed between bit lines to which signals are to be read out of memory cells and a signal transmission line arranged above them are to be reduced. Second complementary global bit lines for transmitting data read out of memory cells MC via complementary bit lines are arranged above a memory cell array. Each second global bit line is so arranged that a triangle having as its vertexes the center of the section of one of the complementary bit lines, that of the section of the other and that of the section of the second global bit line arranged directly above these complementary bit lines be an isosceles triangle.

Semiconductor memory device

A semiconductor device is easy for high accuracy impedance matching against differences in impedance of a transmission line and a package wire. A semiconductor chip having external output buffers and a packaging circuit are included. Each external output buffer has a first output portion whose internal impedance is adjusted commonly with other external output buffers in accordance with impedance control data and a second output portion whose internal impedance is adjusted independently of other external output buffers. Both of the first and second output portions are connected in parallel to a common output terminal. Common adjustment by the first output portion can cope with impedance of the transmission line and individual adjustment by the second output portion can cope with a difference of package wires.

Impedance matching commonly and independently

The present invention provides a semiconductor device that can shorten the initialization cycle of impedance matching of interface buffers and reduce as much as possible affects on other circuits at the time of fine control thereafter. The semiconductor device () includes interface buffers (to) whose internal impedances are controlled by impedance control data and an impedance control circuit () that generates the impedance control data. The impedance control circuit includes a first impedance control mode that initially generates the impedance control data by a binary search and comparison operation resulting from predetermined impedance control steps and sets the impedance control data in the interface buffers, and a second impedance control mode that updates the impedance control data set in the interface buffers by a sequential comparison operation resulting from the predetermined impedance control steps.

Growing community of inventors

Kokubunji, Japan

Hiroki Ueno