Nec Corporation

Japan Display Inc.

Cygames, Inc.

Hiroki Tsuda

Junichi Kobayashi

Susumu Otani

Motoya Iwasaki

Hizuru Nawata

Setomi Uchikawa

Nozomu Shibata

Ryohei Ishizuka

Michiaki Sakaguchi

Koji Nara

Colin Smith

A non-transitory computer readable medium stores a program causing a computer to execute: storing, in a storage unit, a character for which an acquisition condition is satisfied as a possessed character among a plurality of characters including a first character and a second character, each of the plurality of characters including the acquisition condition for acquiring the character, a special ability available in a prescribed game, and a release condition for releasing the special ability; releasing the special ability of the first character when the release condition of the first character is satisfied; releasing the special ability of the second character when the release condition of the second character is satisfied, the acquisition condition of the second character being different from the acquisition condition of the first character, and the release condition of the second character being different from the release condition of the first character; and setting, when the special ability of at least one of the first character and the second character is released, the released special ability so as to be available to other characters in the prescribed game.

Non-transitory computer readable medium, information processing method, and information processing system

According to one embodiment, a liquid crystal display device includes a first substrate including gate lines having a first line width, source lines having a second line width, a common electrode, a sensor electrode formed on the common electrode and having a third line width immediately above the gate lines and a fourth line width less than the second line width immediately above the source lines, and pixel electrodes, a second substrate opposing the first substrate, and a liquid crystal layer held between the first substrate and the second substrate.

Liquid crystal display

According to one embodiment, a liquid crystal display device includes an array substrate, a counter substrate, a liquid crystal layer, and a sealing material. The array substrate includes signal lines, scanning lines, pixel electrodes, and elongated protrusions. The counter substrate includes counter protuberances and a planarization film. Each of the elongated protrusions of the array substrate extends in such a way as to cover a corresponding one of the signal lines and in a rib-like manner along the corresponding signal line. Each of the counter protuberances of the counter substrate is formed integrally with the planarization film and is formed to extend along a direction intersecting a corresponding one of the elongated protrusions. An outer edge of the planarization film is located nearer to a central portion of the liquid crystal display device than an inner edge of the sealing material.

Liquid crystal display device having an array substrate with elongated protrusions

According to one embodiment, a liquid crystal display device includes a driving module configured to apply a DC bias to a voltage corresponding to a gradation which is displayed on a pixel and to supply a resultant voltage to a pixel electrode, the driving module being configured to apply a higher DC bias in a white display state in which a potential difference is produced between a pixel electrode and a common electrode than in a black display state in which no potential difference is produced between the pixel electrode and the common electrode.

Liquid crystal display device and method of driving the same

A first substrate includes a first switching element arranged in a first color pixel and a second switching element arranged in a second color pixel of which color is different from the color of the first color pixel in an active area. A driving unit superimposes DC bias voltages on voltages corresponding to gradations to be displayed in the first color pixel and the second color pixel, and to supply the superimposed voltages to the first pixel electrode and the second pixel electrode, respectively. A first halftone gradation voltage obtained by superimposing a first DC bias voltage on a voltage corresponding to a halftone gradation is supplied to the first pixel electrode. A second halftone gradation voltage obtained by superimposing a second DC bias voltage different from the first DC bias voltage on a voltage corresponding to the halftone gradation is supplied to the second pixel electrode.

A memory access method and system which solve the problems of degradation of data transfer efficiency due to memory access waiting period and complexity of memory interface. The system has an address buffer for reading an address in synchronization with a clock, and a burst counter which generates an address of burst length. Further, a ROW address register adjusts timing by latching a ROW address, and similarly a COLUMN address register adjusts timing by latching a COLUMN address. A ROW address decoder decodes the ROW address while a COLUMN address decoder sets the decodes the COLUMN address. The system also includes a mode register which sets the operation mode of the DRAM and a command decoder which interprets and discriminates a command signal. Finally, a controller controls the operation of the overall DRAM, and a memory array holds data for use with a data input/output buffer for data transmission/reception.

Memory access method and system for writing and reading SDRAM

In a mobile satellite communications system comprising an earth station (,), a mobile station (,) with a mobile antenna (,), and a communication satellite (,) for mediating communications between the earth station and the mobile station, the earth station comprises a carrier frequency variation detecting device (,) for detecting a received carrier frequency due to a doppler effect to produce a frequency variation detected signal. Although an earth signal processing circuit (,) transmits a burst carrier signal or a maintaining burst signal to the mobile station when an information signal such as a speech signal to be transmitted is not supplied thereto, the earth signal processing circuit extends a burst transmission duration for the maintaining burst signal in response to the frequency variation detected signal and it results in making the mobile station easily carry out antenna tracking control. In addition, the earth signal processing circuit continuously transmits the carrier signal when a received frame synchronization is pulled out.

Mobile satellite communication method and system capable of carrying out carrier activation with reliability of a communication path secured

The invention provides a transmission power control apparatus for a mobile radio satellite communication system which allows frame synchronization maintenance and synchronization acquisition of a receiving station and optimum transmission power control with a simple construction which does not effect complicated control. The transmission power control apparatus includes a transmission power control loop provided in each of a gateway station and a terminal/mobile station for controlling a transmission power of the station. The transmission level during transmission is monitored and compared with a preset transmission level to change over an average time for sampling of the error between the transmission levels to vary the response speed of the transmission power control loop. When the channel for current use is to be changed over from a signalling channel to a communication channel, the transmission power is controlled so that there is no trouble for continuous synchronization of the reception side. But, when the channel is to be changed over from the communication channel to the signalling channel, the transmission power is controlled rapidly to a standard level so that there is no trouble in synchronization acquisition or data transmission.

Transmission power control method and apparatus for mobile radio

A mobile station comprises a power detector, an averaging circuit, and a signal fade detector. The power detector measures a channel signal power (receive signal power) of a receive signal received by a receiver. The averaging circuit averages the receive signal power measured by the power detector. The signal fade detector detects the fade of the channel signal power with the average of the receive signal power. When the fade of the receive signal is detected, while a call request or a call response is being transmitted, after the receive signal power is recovered, a control circuit of the mobile station re-transmits the call request or the call response. When the fade of the receive signal is detected just before a call request or a call response is to be transmitted, the control circuit of the mobile station stops transmitting the call request or the call response. After the receive signal power is recovered, the control circuit of the mobile station transmits the call request or the call response.

Demand-assigned satellite communications system

The present invention refers to a received signal detector for detecting and demodulating a digital modulated signal wherein a signal detection in a short time can be implemented independently of the signal frame length. The wide-band filter is a filter having a pass frequency band set to the frequency range of received signals to be demodulated. The A/D convertor, first power detector and first averaging circuit measure the average power of a signal having passed through the wide-band filter. The threshold setting circuit sets a threshold from the averaged power. The narrow-band filter filters an output signal of the frequency convertor in a narrower frequency band than the pass frequency band of the wide-band filter. The comparator circuit compares the threshold and the average power of a signal taken out from the second averaging circuit and passing through the narrow-band filter and judges whether the received signal is taken out from the wide-band filter.

Received signal detector for digital demodulator

In a PSK signal demodulation method of demodulating a received signal by sampling processing, one sampling interval is time-divided. A received signal is detected in different carrier frequency offset ranges in the respective time-division intervals. Reception processing is continuously performed in only a time-division interval in which the received signal is detected after the received signal is detected, thereby synchronizing carrier phase. A PSK signal demodulation apparatus is also disclosed.

PSK signal demodulation method and apparatus

An apparatus and method for establishing frame synchronization in a satellite communication system which receives a modulated signal having frames, such that a unique word and data are multiplexed in each of the frames. A demodulator demodulates the modulated signal and provides a demodulated signal including the unique words. A signal detector compares the signal power of the demodulated signal with a threshold signal and provides a detection signal. A selector provides, in accordance with the detection signal, the detected demodulated signal or fixed data as a selected signal. A frame synchronizing circuit detects the unique word from the selected signal, when the demodulated signal is provided as the selected signal by the selector, and establishes frame synchronization in accordance with the detected unique word.

Method and apparatus for establishing and maintaining frame

In a PSK-modulating arrangement including a voltage controlled oscillator (VCO), a demodulator, a phase detector and a loop filter, a carrier phase lock detecting apparatus is equipped with the arrangement, the apparatus comprising a first multiplier for inversely modulating a demodulated signal by a reference carrier signal from the VCO, a second multiplier for multiplying the output of the first multiplier by an input PSK-modulated signal and a decision circuit for detecting carrier phase lock in response to the output of the second multiplier.

Carrier phase lock detecting apparatus used in PSK-modulated signal

An intermittently transmitted burst modulation signal is demodulated to a baseband signal and multiplied with a variable gain coefficient. A range where a difference signal of a power signal of the multiplied signal from a reference power level is included, in a plurality of level ranges, is decided. A loop constant is determined in accordance with the decided range and is multiplied with the difference signal. An integrated multiplied difference signal with the loop constant is used for changing the variable gain constant.

AGC circuit for burst signal

In a demodulator, a delay detection means receives a .pi./4-shift QPSK signal and performs delay detection of a signal at an interval of symbols. An averaging circuit respectively averages two channel quadrature signal components of a signal. A preamble detection means detects a preamble having a specific pattern in which a phase shift of .pi./4 of the phase of a received symbol from the immediately preceding symbol and a phase shift of -3.pi./4 of a phase of a next symbol from the immediately preceding symbol are alternately repeated on a phase plane of the two channel quadrature signal components. A phase angle calculating means calculates the phase angle of an output signal from the averaging circuit. A frequency offset estimating circuit calculates a carrier frequency offset. A voltage-controlled oscillator has an output oscillation frequency variably controlled by an output signal from the frequency offset estimating circuit. A frequency converter performs frequency conversion of the output oscillation frequency of the voltage-controlled oscillator and the input .pi./4-shift QPSK signal. A reproduction circuit reproduces a carrier and a clock from an output .pi./4-shift QPSK signal from the frequency converter, and obtains demodulated data by coherent detection.

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Tokyo, Japan

Hiroki Tsuda