Matsushita Electric Industrial Co., Ltd.

Panasonic Corporation

Hiroki Tomoshige

Kenichi Tajika

Isao Motegi

Minoru Itoh

Noriko Oosuka

Satoru Nishioka

Tarou Fukunaga

Mie Yamanaka

Masaki Ishino

Maya Ishino

Mitsukiyo Matsui

Muneaki Kyoya

To provide a pattern correction apparatus which enables easy correction of a trace which is not present on trace grids, a pattern correction apparatus which makes a correction to a pattern of an integrated circuit includes a trace movement section for moving, among traces forming the pattern of the integrated circuit, a trace which is not present on trace grids to a position above the trace grids; a pattern correction section for making a correction to the pattern; and a trace pitch optimization section for optimizing a trace pitch between traces forming a pattern corrected by the pattern correction section.

Pattern correction apparatus, pattern optimization apparatus, and integrated circuit design apparatus

In a standard cell synthesizing step, a net list is synthesized from an RTL description, and an instance name list is formed which contrasts a register description portion with an instance name contained in the net list; in a simulation step, an operation simulation written by the RTL description is carried out; the toggle information among registers which is extracted in the simulation stepis recorded in a toggle storing step, a flip-flop-to-flip-flop toggle information database is constructed in which the recorded toggle information corresponds to a flip-flop-to-flip-flop instance name obtained from the instance name list in a mapping step; and in an electric power optimizing step, a physical designing operation for reducing power consumption is optimized by employing the net list, the flip-flop-to-flip-flop toggle information database, and a timing restriction.

Low power consumption designing method of semiconductor integrated circuit

In a clock delay adjusting method of a semiconductor integrated circuit device, a plurality of source points for adjusting a clock delay is provided to synchronize a value of the clock delay from each of the source points of each of hierarchical blocks in a semiconductor chip to a clock input circuit operating synchronously with a clock, according to circuit design conditions of the hierarchical blocks. Area terminals are provided in the source points, respectively. A clock input terminal of the semiconductor chip and each area terminal are connected through a clock line so as to be clock distributed over a hierarchical top. A clock delay between the hierarchical blocks is adjusted.

Clock delay adjusting method of semiconductor integrated circuit device and semiconductor integrated circuit device formed by the method

Growing community of inventors

Kanagawa, Japan

Hiroki Tomoshige