Nec Corporation

Astellas Pharma Gmbh

National Cancer Center

Hiroki Shirai

Kazunori Hirayama

Akifumi Morinaka

Hitoshi Doihara

Takeshi Okazawa

Naomi Hosogai

Hirohito Watanabe

Ichiro Honma

Taishi Kubota

Haruhiko Ono

Hiroki Sasaki

Shigenori Yagi

Masayuki Komatsu

Hiroyoshi Yamada

Ken-Ichi Oyama

Nobuyuki Shiraishi

Toru Asano

Yoshiyuki Tenda

Michinori Akaiwa

Yorikata Sano

Masatoshi Yuri

Yoshiki Satake

Fumiko Chiwaki

An object of the present invention is to provide an anti-CLDN4/anti-CD137 bispecific antibody usable in treatment of cancer. An anti-CLDN4/anti-CD137 bispecific antibody produced using an anti-CLDN4 antibody binding to CLDN4 and an anti-CD137 antibody binding to CD137 had agonistic activity for CD137, promoted production of interferon γ by a T cell, and exhibited cytotoxic activity against a cancer cell expressing CLDN4 on a cell surface thereof. Besides, it was shown that the anti-CLDN4/anti-CD137 bispecific antibody can be safely administered to monkeys. Therefore, the anti-CLDN4/anti-CD137 bispecific antibody is usable in treatment of human cancer.

Anti-CLDN4/anti-CD137 bispecific antibody

Provided are a conjugate comprising an anti-human MUC1 antibody Fab fragment and a peptide linker and/or a ligand, a composition for diagnosis and/or a pharmaceutical composition comprising the conjugate, a method for diagnosing and/or treating a cancer using the conjugate, and the like. In the conjugate used, the anti-human MUC1 antibody Fab fragment is bound to the ligand via the peptide linker or the like.

Complex having anti-human MUC1 antibody Fab fragment, peptide linker and/or ligand

The problem to be solved is to provide an anti-human MUC1 antibody Fab fragment that is expected to be useful in the diagnosis and/or treatment of a cancer, particularly, the diagnosis and/or treatment of breast cancer or bladder cancer, and a diagnosis approach and/or a treatment approach using a conjugate comprising the Fab fragment. The solution is an anti-human MUC1 antibody Fab fragment comprising a heavy chain fragment comprising a heavy chain variable region consisting of the amino acid sequence represented by SEQ ID NO: 8 or 10, and a light chain comprising a light chain variable region consisting of the amino acid sequence represented by SEQ ID NO: 12, and a conjugate comprising the Fab fragment.

Anti-human MUC1 antibody Fab fragment

Provided are an anti-human CEACAM5 antibody Fab fragment expected to be useful in the diagnosis of a cancer, particularly, the diagnosis of colorectal cancer, breast cancer, lung cancer, thyroid gland cancer or a cancer resulting from the metastasis thereof, and a diagnosis approach using a conjugate comprising the Fab fragment. The present invention provides an anti-human CEACAM5 antibody Fab fragment comprising a heavy chain fragment comprising a heavy chain variable region consisting of the amino acid sequence represented by amino acid positions 1 to 121 of SEQ ID NO: 2, and a light chain comprising a light chain variable region consisting of the amino acid sequence represented by amino acid positions 1 to 112 of SEQ ID NO: 4, and a conjugate comprising the Fab fragment.

Anti-human CEACAM5 antibody Fab fragment

Anti-human MUC1 antibody fab fragment

The present invention provides a method of forming a gate structure of a floating gate MOS field effect transistor. The method comprises the steps of: forming a conductive layer on a gate insulating film; forming a dummy layer over the conductive layer; selectively forming a resist pattern over the dummy layer; carrying out an anisotropic etching process for patterning the dummy layer and the conductive layer by use of the resist pattern as a mask, thereby to form a gate structure removing the resist pattern; forming side wall insulation films on side walls of the gate structure; forming an inter-layer insulator so that the gate structure and the side wall insulation films are completely buried within the inter-layer insulator; carrying out a first planarization process for polishing the inter-layer insulator; and carrying out a second planarization process for selectively etching the inter-layer insulator and the side wall insulation films, so that at least a top portion of the dummy layer is etched; removing the dummy layer; carrying out a third planarization process for selectively etching the inter-layer insulator and the side wall insulation films, so that a planarized surface of the inter-layer insulator and the side wall insulation films is leveled to a planarized surface of the conductive layer, wherein the dummy layer has a higher etching selectivity to the inter-layer insulator than nitride.

Method of forming a highly integrated non-volatile semiconductor memory device

There are disclosed a nonvolatile semiconductor memory device, which is capable of maintaining a high capacitance ratio even when a memory cell is formed in a micronized size without increasing the number of manufacturing steps, and its manufacturing method. In a flash memory having buried diffusion layer type cells, a source region and drain regions and are formed in self alignment with a polycrystalline film pattern which has a polycrystalline silicon film having projecting and recessing parts in its upper surface.

Nonvolatile semiconductor memory device and manufacturing method of the

There is disclosed a nonvolatile semiconductor memory device, which is capable of maintaining a high capacitance ratio even when a memory cell is formed in a micronized size without increasing the number of manufacturing steps. In a flash memory having buried diffusion layer type cells, a source region and drain regions and are formed in self alignment with a polycrystalline film pattern which has a polycrystalline silicon film having projecting and recessing parts in its upper surface.

A non-volatile semiconductor memory cell comprises a source region having an N.sup.+ type diffusion layer, an N.sup.- diffusion layer, and N type diffusion layer, the N.sup.- type diffusion layer being formed by injecting phosphorus ions by an inclined rotating ion injecting method. The overlap width of the N.sup.- type diffusion layer and the floating gate electrode is larger than the overlap width of the N.sup.+ type diffusion layer and the floating gate electrode, and the junction depth of the N type diffusion layer is larger than the junction depth of the N.sup.+ type diffusion layer. Thus, in flash memory having memory cells according to the present invention, even if the size of the memory cells is reduced, erase time can be shortened without sacrificing erase function and performance.

Non-volatile semiconductor memory cell

Disclosed is an electrically erasable nonvolatile semiconductor memory device having a floating gate electrode formed on a semiconductor substrate through a first gate insulating film, a control gate electrode formed on the floating gate electrode through a second gate insulating film, and source and drain regions spaced apart from each other under the floating gate electrode so as to partially overlap the floating gate electrode, wherein an electric field buffering means for relaxing an electric field generated between a peripheral portion of an element isolation region and an end portion of the floating gate electrode in application of an erase voltage is selectively formed as a lightly doped region in a source region surface portion of the peripheral portion of the element isolation region.

Nonvolatile semiconductor memory device having electric field buffering

A method of controlling the nonvolatile memory device comprising making over-erasing simultaneously a set of EEPROM elements and then setting simultaneously the threshold voltages of said set of EEPROM elements back to the specified threshold-voltage values. The over-erasing is accomplished by applying a first pulse between the source and the control gate to induce the first FN current across the gate insulating film. The setting-back is accomplished by applying a second pulse between the well and the control gate to induce the second FN current flowing reversely to the first FN current.

Growing community of inventors

Tokyo, Japan

Hiroki Shirai