Matsushita Electric Industrial Co., Ltd.

Hiroki Shinde

Kimiaki Ando

Shouichi Kobayashi

Hiroshi Mizuno

Toshiyuki Moriwaki

Isao Motegi

Mikawa Takahashi

A wireless communication apparatus capable of minimizing a danger involved in transmit power control based on control information containing errors and securing reliability of a system. In this apparatus, an overflow error detector and a reception state monitoring section acquire information on overflows of the analog to digital converter. Then, the reception quality decision section evaluates reliability of the received signal considering this overflow information and removes the signal with a reliability determined to be low from the basic data for generation of transmit power control information.

Method for controlling generation of transmission power control information, method of controlling characteristics of receiver circuit based on overflow information, and CDMA communication apparatus

The pilot signal reception method of the present invention irregularly receives pilot symbols. That is, the pilot signal reception method performs irregular reception processing such as randomizing reception timings or changing reception timings according to reception situations as appropriate to reduce influences of fading. Randomization of reception timings is implemented by generating random timings using a random timing generation circuit.

Pilot signal reception method and receiver

A design technique considering a peak current is provided for high-level design of systems including LSIs. A hardware model representing the trade-off relationship between a leak current and performance is prepared in advance for functional units constituting the system. In the hardware model, the relationship between performance tpd and a source-drain leak current Pleak is described with a threshold voltage Vth as a parameter, for example. By referring to the trade-off relationship, design conditions for the functional units are determined under evaluation of the performance and power consumption of the entire system.

Method for designing LSI system

A transmission power control apparatus for outputting a transmission data to be filtered by a band-limiting filter (), includes: a branching unit () for branching transmission data before being entered into the band-limiting filter (); a peak detecting filter () having the same structure as that of the band-limiting filter (), for entering thereinto one of the transmission data branched by this branching unit (); units (to) for calculating a correction value capable of suppressing a power peak of the transmission data by being filtered by this peak detecting filter (); a delaying unit for delaying the other data of the branched transmission data by time required to calculate the correction value; and a correcting unit () for correcting the transmission data delayed by this delaying unit () based upon the correction value, and thereafter, for entering the corrected transmission data into the band-limiting filter ().

Transmission power control method and apparatus, and communication apparatus

A limiting method is provided which limits signals having two components I channel and Q channel on two orthogonal coordinate axes within a predetermined range on the coordinate plane specified by the two coordinate axes, wherein the predetermined range is defined by concentric circles having the origin of the two coordinate axes as a center.

Limiting method and limiter apparatus

A transmission system is featured by that a correcting unit is arranged at a prestage of an ROF unit in the CDMA system. In this transmission system, an instantaneous power amount is calculated, and is compared with a preset upper limit value. When this calculated instantaneous power amount exceeds this upper limit value, this power amount is detected as an instantaneous peak. Only when the calculated instantaneous power amount exceeds the upper limit value, an amplitude correction is selectively carried out so as to reduce distortions appeared in the vicinity of a region to be corrected.

Transmission band limiting filter apparatus and transmission apparatus

An amplitude detecting circuit ( ) includes a simple digital filter ( ) having a structure corresponding to a part where the energy is concentrated in the full impulse response of a signal processing digital filter ( ). Concretely, for example, the amplitude detecting circuit ( ) (simple digital filter ( )) includes only four central taps having coefficients of large absolute values and considerably affecting on the output amplitude among sixteen taps of the signal processing digital filter ( ). By the amplitude detecting circuit ( ), the amplitude of an output signal of the signal processing digital filter ( ) can approximately be detected.

Amplitude detecting circuit

An apparatus for obtaining correlation by despreading a spread symbol with a spreading code is provided with a symbol storage section for storing symbol and a plurality of correlation calculators each of which executes a correlation calculation to obtain correlation by despreading the symbol data with a spreading code. The apparatus switches a spreading code to be provided to each of the plurality of correlation calculators individually so that each of the plurality of correlation calculators executes correlation calculation with a respective different spreading code and holds a same spreading code until correlation calculations of a plurality of symbols are finished.

Correlation detection apparatus and CDMA receiving apparatus

An address generator for compensating non-linear distortion of a transmitting amplifier according to this invention comprises transmission power calculation means for calculating transmission power based on transmission data, a comparator control circuit, and an address generation table. The address generation table comprises a plurality of comparators operating in parallel. The comparator control circuit turns on only necessary comparators based on the transmission power value so as to reduce power consumption.

Distortion compensation address generator, distortion compensating circuit, and transmitter

A digital filter according to the invention is an x-time interpolation (x is an interpolation ratio) type FIR filter. The digital filter is provided with a plurality of stages of delay elements into which serial data are inputted, and a plurality of data distributors which distribute the respective output data of the plurality of stages of delay elements into x different signal channels by a time-sharing system. The respective data distributors operate a rate higher by x times than the input rate of serial data and distribute data into x different channels by time-sharing. Preferably, by utilizing the symmetry of a digital filter coefficients, only the digital filter coefficients corresponding to the half taps at one side of the digital filter are prepared, wherein the respective output data of a pair of delay elements located at the symmetrical positions are inputted into one data distributor, and the respective data are distributed by a time-sharing system.

Digital filter, digital signal processing method, and communication apparatus

Consumption power is reduced in a digital matched filter for determining a correlation value between a digital signal (I,) of 6 bits, which is synchronous with a clock, and a despreading code sequence (C,C,C,C,C,C,C,C,) which includes 8 despreading codes. First to eighth flip-flop sets (,) constituting a storage section (,) are sequentially selected clock by clock by a write selection circuit (,), and the digital signal (I,) is stored in the selected flip-flop set. The 8 despreading codes are stored in first to eighth code flip-flops (,), respectively, and are shifted in synchronism with the clock. Output signals of the first to eighth flip-flop sets are multiplied by output signals of the first to eighth code flip-flops in first to eighth multiplication circuits (,), respectively.

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Yokohama, Japan

Hiroki Shinde