Toshiba Tec Kabushiki Kaisha

Hitachi, Ltd.

Kabushiki Kaisha Toshiba

Audio-technica Corporation

Hiroki Satoh

Koji Tanimoto

Makoto Nakajima

Toshiomi Moriki

Takaharu Ishida

Miho Kobayashi

Yuuichi Kurosawa

Alexander Lepges

A control device is a control device for controlling a plurality of receiver devices for receiving a sound signal transmitted from a wireless microphone by radio, the control device includes an information acquisition part that acquires quality information indicating a quality of the sound signal received by the plurality of receiver devices, and a determination part that determines, on the basis of the quality of the sound signal indicated by the quality information, a non-output receiver device that does not cause a speaker to output the sound based on the sound signal out of the plurality of receiver devices.

Control apparatus, computer readable medium and microphone system

An application executed at a user terminal with a touch screen displays, on the touch screen, a UI in which a user-side UI for accepting a touch operation by a user and a store-side UI for accepting a touch operation by a staff member of a store are placed, as a settlement UI for settlement of a currency amount of a digital local currency. The application judges whether time during which the touch operation on the user-side UI and the touch operation on the store-side UI are simultaneously continued has reached a specified period of time or not. If the judgment result is true, the application displays a settlement completion notice on the touch screen.

Method and system for supporting promotion of use of digital local currency

A communicating unitof a power interchange management systemis coupled to a plurality of power interchange apparatusesthat control electrical equipmentto. Each power interchange apparatus is coupled via a system power supply line. A computing unitcreates a group for interchanging power by acquiring prescribed pieces of informationtofrom the respective power interchange apparatuses and selecting a plurality of prescribed power interchange apparatuses based on the prescribed pieces of information. Prescribed conditions include a condition related to control power. The condition related to control power may be that a first power interchange apparatus on a power transmitting side has power for power transmission control necessary for transmitting power and, at the same time, a second power interchange apparatus on a power receiving side has power for power reception control necessary for receiving power.

Power interchange management system and power interchange management method for maintaining a balance between power supply and demand

According to an equalizing circuit and an equalizing method, a memory control unit receives an input of an input image data signal, a first memory stores the input image data signal after delaying it and a CPU designates at least any one of a main scan coordinate and a subscan coordinate to start equalizing of the input image data signal, a main scan size and a subscan size of the equalized block and skew values in a main scan direction and in a subscan direction of the equalized block. Then, a register setting unit holds the setting information which is designated by the CPU and an equalizing control unit performs the equalizing of the input image data signal at a certain timing independently of a skew value of the equalized block on the basis of the setting information held by the register setting unit and outputs the equalized image data signal. Thus, a second memory receives an input of the equalized image data signal from the equalizing control unit and holds it as an output image data signal and an output control unit outputs the output image data of the second memory.

Equalizing circuit and method, and image processing circuit and method

When a CPU begins to monitor whether delay variation characteristics of a pulse width variation circuit have varied, it selects a basic delay setting value in a basic delay value setting block from a smallest one. The CPU sets a division number in a phase select block from a given minimum desired division number for pulse width modulation. The CPU senses the level of a phase comparison result signal (PHASE) from the pulse width modulation circuit. If the phase comparison result signal is stable at &ldquo;1&rdquo;, the CPU fixes the division number. If the phase comparison result signal is &ldquo;0&rdquo; and the division number is not maximum, the CPU increases the division number and goes back to the setting of the division number. If the division number is maximum, the CPU increases the basic delay and goes back to the basic delay setting.

Pulse width modulation system and image forming apparatus having the pulse width modulation system

When a CPU begins to monitor whether delay variation characteristics of a pulse width variation circuit have varied, it selects a basic delay setting value in a basic delay value setting block from a smallest one. The CPU sets a division number in a phase select block from a given minimum desired division number for pulse width modulation. The CPU senses the level of a phase comparison result signal (PHASE) from the pulse width modulation circuit. If the phase comparison result signal is stable at &ldquo;1&rdquo;, the CPU,fixes the division number. If the phase comparison result signal is &ldquo;0&rdquo; and the division number is not maximum, the CPU increases the division number and goes back to the setting of the division number. If the division number is maximum, the CPU increases the basic delay and goes back to the basic delay setting.

Growing community of inventors

Tokyo, Japan

Hiroki Satoh