Kabushiki Kaisha Toshiba

Toshiba Memory Corporation

Hiroki Okamoto

Masayuki Kitamura

Hiroyuki Kutsukake

Takashi Izumida

Atsushi Yagishita

Akira Hokazono

Hiroshi Itokawa

Yoshiaki Shimooka

Kiyoshi Okuyama

An integrated circuit device includes a first and a second semiconductor regions, a first electrode provided above the first semiconductor region, a second electrode provided above the second semiconductor region, a first and a second interconnects. The first and the second semiconductor regions are arranged to be separated from each other in a first direction. Longitudinal directions of the first and second semiconductor regions are a second direction. Longitudinal directions of the first and second electrode are a third direction. The first and second interconnects extend in the first direction and are provided in a region including a region directly above the first electrode and a region directly above the second electrode. The first interconnect is connected to the first electrode. The second interconnect is connected to the second electrode.

Integrated circuit device

A memory device includes a first interconnect extending in a first direction, a first and a second semiconductor members extending in a second direction, a first and a second gate lines extending in a third direction, a second and a third interconnects extending in the second direction. The first and the second semiconductor members are arranged along the first direction, with first ends in the second direction connected to the first interconnect. The second interconnect is connected to a second end in the second direction of the first semiconductor member. The third interconnect is connected to a second end in the second direction of the second semiconductor member. The distance between the first interconnect and the first gate line is longer than the distance between the first interconnect and the second gate line.

Memory device

According to one embodiment, the contact electrode extends in the inter-layer insulating layer toward the second semiconductor region. The metal silicide film is in contact with the second semiconductor region and the contact electrode. The metal silicide film includes a first part and a second part. The first part is provided between a bottom of the contact electrode and the second semiconductor region. The second part is provided on a surface of the second semiconductor region between the first part and the gate electrode. A bottom of the second part is located at a position shallower than a bottom the first part.

Semiconductor device and method for manufacturing the same

A semiconductor device may include a p-channel semiconductor active region and an n-channel semiconductor active region. An element isolation insulating layer electrically isolates the p-channel semiconductor active region from the n-channel semiconductor active region. An insulating layer made of a different material, being in contact with both ends, in its channel length direction, of the p-channel semiconductor active region applies a compression stress in the channel length direction to a channel of the p-channel semiconductor active region. The p-channel semiconductor active region is surrounded by the insulating layer, in the channel length direction, of the p-channel semiconductor active region and by the element isolation insulating layer, parallel to the channel length direction, of the p-channel semiconductor active region. The n-channel semiconductor active region is surrounded by the element isolation insulating layer.

Semiconductor device

A semiconductor device according to an embodiment includes: a semiconductor substrate; a gate electrode formed on the semiconductor substrate via a gate insulating film; a channel region formed in a region of the semiconductor substrate below the gate electrode; an epitaxial crystal layer containing a conductive impurity, which is formed sandwiching the channel region and has a function as a source region and a drain region, and formed on a recess in the semiconductor substrate; and a growth suppressing portion formed on the recess in the semiconductor substrate, and configured to suppress an epitaxial growth of a crystal in the epitaxial layer from the semiconductor substrate.

Growing community of inventors

Nishinomiya, Japan

Hiroki Okamoto