Fujitsu Corporation

Hiroki Narita

Aiichiro Inoue

An instruction processing apparatus using a microprogram instruction which implements re-reading operation. The instruction execution apparatus is provided with a queue stack, a unit halting requests for reading subsequent instructions at the instruction of a microprogram, and a unit releasing this halt. Further, by instruction the reading of the subsequent instructions using the microprogram control information, it becomes possible to simultaneously execute the microprogram and instruction re-reading processing. Because the Program Status Word Instruction Address (PSWIAR) of the load control (LCTL) plus the instruction length of the PSWIAR makes an instruction fetch address of the LCTL, the hardware of the instruction re-read address production circuit (which is a part of the instruction processing circuit) can be used. This reduces the: T-cycle instruction address register (TIAR), T-cycle instruction length code (TILC), A-cycle instruction address register (AIAR), the A-cycle instruction length code (AILC), and an adder for adding the TILC with the TIAR.

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Kawasaki, Japan

Hiroki Narita