Kabushiki Kaisha Toshiba

Pilkington Micro-electronics Limited

Hiroki Muroga

Satoshi Suzuki

Nobutaka Kitagawa

Yukihiro Saeki

Tomotaka Saito

Kenneth Austin

Tomohisa Shigematsu

Hiroyuki Motegi

Gordon S Work

Yasuo Kawahara

Takao Shijo

Kazunao Maru

Fumio Sudo

Toshio Hibi

Darren M Wedgwood

There is disclosed a functional block which comprises a function portion, a plurality of block input terminals, a plurality of block output terminals, a first signal holding circuit group connected between inputs of the function portion and the plurality of block input terminals, and a second signal holding circuit group connected between outputs of the function portion and the plurality of block output terminals. Since the first signal holding circuits and the second signal holding circuits receive a clock signal supplied externally to the functional block and then operate to synchronize with the clock signal respectively, a delay time of output signals for input signals in the functional block can be easily estimated. Hence, simulation of a semiconductor integrated circuit constructed by combining a plurality of functional blocks can be easily performed.

Functional block and semiconductor integrated circuit architected by a plurality of functional blocks in combination

A programmable logic unit circuit comprising a data memory circuit, a combinational logic circuit supplied with at least two input signals, two input select circuits for, based on the stored data in the data memory circuit, selecting the two input signals supplied to the combinational logic circuit from more than two input signals, a clock-synchronized circuit for supplying the output signal from the combinational logic circuit in synchronization with a clock signal, and a 3-state-output type output select circuit for selecting either the output signal of the combinational logic circuit or the output signal of the clock-synchronized circuit, depending on the stored data in the data memory circuit.

Configurable logic element with independently clocked outputs and node

An integrating circuit integrates an input signal. When an output from the integrating circuit is input to an AC coupling circuit, only an AC component of the output is extracted. The AC component which passes through the AC coupling circuit is waveshaped and coverted into a rectangular wave by a waveshaping circuit. The duty ratio of the waveshaped rectangular wave is detected by a duty ratio detecting circuit. A voltage corresponding to the duty ratio is then generated and fed back to the output of the AC coupling circuit through a feedback circuit. As a result, a DC bias component is applied to the AC component which has passed through the AC coupling circuit. In this case, the voltage generated by the duty ratio detecting circuit is controlled to coincide with the circuit threshold value of the waveshaping circuit, and a rectangular wave having a duty ratio of 50% is output from the waveshaping circuit.

Duty radio control circuit apparatus

Diffusion layers are formed in a surface region of an N-type substrate. The diffusion layers are interconnected by means of an Al wiring layer. A P-well is formed in the substrate. A power source potential is connected to the substrate and a reference potential is connected to the P-well 17. The Al wiring layer is connected to the power source potential via the substrate to detect the power source potential.

Substrate potential detecting circuit

A voltage controlled oscillator (VCO) is controlled by a separate phase locked loop (PLL). The PLL includes a first variable delay circuit of m stages which receives a reference frequency signal and produces a delayed signal which is compared in a phase comparator with the reference frequency signal. A first control signal generating circuit in the PLL receives the output of the phase comparator and a reference voltage to produce a first control signal for controlling the delay of the first variable delay circuit. The VCO contains a ring oscillator formed of a second variable delay circuit of n stages similar to those of the first variable delay circuit. A second control signal generating circuit in the VCO receives the output of the phase comparator and a control voltage to produce a second control signal for controlling the delay of the second variable delay circuit to thereby control the output frequency of the VCO.

VCO controlled by separate phase locked loop

Growing community of inventors

Yokohama, Japan

Hiroki Muroga