Winbond Electronics Corporation

Fuji Xerox Co., Ltd.

Spansion Llc.

Windbond Electronics Corp.

Samsung Electronics Co., Ltd.

Fujitsu Corporation

Hiroki Murakami

Makoto Senoo

Kazuhiro Kurihara

Yasuhiro Uehara

Mitsuhiro Matsumoto

Junji Okada

Hideaki Ohara

Mikio Saiki

Kengo Shinozaki

Kimihiro Wakabayashi

Tadashi Suto

Masaaki Lawrence Araki

Kazuyoshi Ito

Kimiyuki Kawakami

Masaru Yano

Kazuki Yamauchi

Kenichi Arakawa

Katsushi Aoki

Junya Yamasaki

Atsushi Shimizu

Hiroshi Inoue

Takashi Ozawa

Eric Alan Merz

Masaki Kataoka

Tohru Inoue

Masao Funada

Brian S Hilton

Makoto Hirano

Tomoya Ichikawa

Kuniaki Tanaka

Nobuyoshi Komatsu

Tsutomu Sugimoto

Yoshitaka Kuroda

Shigeo Ohno

Hiromi Nagai

Yasuo Takayama

Yoji Yamaguchi

Masao Kuriyama

Takatoshi Tsuchiya

Hidemitsu Kojima

Masafumi Nakatani

Takahiro Shinkawa

Yuichiro Nakagaki

Takahiro Toda

Shinichi Iida

Disclosed is a voltage generating circuit including a reference voltage generating part, a leakage current monitoring part, a control part, and an internal voltage generating part. The reference voltage generating part generates a reference voltage. The leakage current monitoring part generates a monitoring leakage current corresponding to a leakage current of an internal circuit of a semiconductor device. The control part controls the reference voltage according to the monitoring leakage current. The internal voltage generating part receives the reference voltage being controlled by the control part, and supplies an internal voltage to the internal circuit according to the controlled reference voltage. A semiconductor device including the same is also disclosed.

Voltage generating circuit and semiconductor device for suppressing leakage current

The present invention provides an oscillator circuit and a semiconductor integrated circuit, which can suppress the upper limit of the frequency of a clock signal due to an error of the constant current circuit. The oscillator circuit of the present invention includes a constant current circuit, an oscillator, and a current limiting circuit. The constant current circuit generates a first output current according to a supply voltage. The current limiting circuit receives the first output current and generates a second output current, and establishes an upper limit for the second output current when the supply voltage drops below a lower limit of a guaranteed operational range of the constant current circuit. The oscillator generates a clock signal according to the second output current. By establishing the upper limit for the second output current, the upper limit of the frequency of the clock signal can be suppressed.

Oscillator circuit and semiconductor integrated circuit

The invention provides a voltage-generating circuit with a simple configuration capable of saving space and generating reliable voltage. The voltage-generating circuit of the invention includes a reference voltage-generating unit, a PTAT voltage-generating unit, a comparison unit, and a selection unit. The reference voltage-generating unit generates a reference voltage essentially without dependency on temperature. The PTAT voltage-generating unit generates a temperature-dependent voltage with a positive or negative dependency on temperature. The temperature-dependent voltage is equal to the reference voltage at a target temperature. The comparison unit compares the reference voltage with the temperature-dependent voltage. The selection unit selects and outputs either the reference voltage or the temperature-dependent voltage.

Voltage-generating circuit and semiconductor device using the same

A reference voltage generation circuit of the invention includes: PMOS transistors Pand Pconfigured to provide current sources with same current to a first current path and a second current path; a bipolar transistor Qconnected to the PMOS transistors Pon the first current path; a bipolar transistor Qconnected to the PMOS transistors Pon the second current path; a differential amplifier AMP controlling the gates of the PMOS transistors Pand P, such that a voltage of a node VN and a voltage of a node VP are equal; an output node BGR outputting a reference voltage Vref; and a reference voltage guarantee portionoutputting a detecting signal BGRDET when a differences between the voltage of the node VN and the voltage of the node VP is maintained below a determined value.

Reference voltage generation circuit, power-on detection circuit, and semiconductor device for preventing internal circuit from operating incorrectly at low voltage

A protection method is provided to make it difficult to reverse engineer operational information. The present invention provides a protection method for preventing reverse engineering, including: generating an expected value during normal operation; monitoring voltage waveforms at monitoring points of the semiconductor integrated circuit; comparing a measured value generated in the monitored voltage waveforms with the expected value; determining whether reverse engineering is taking place or not based on comparison results; and when reverse engineering is taking place, controlling the semiconductor integrated circuit to run in a protection mode, which different from its normal operation.

Method and semiconductor device for protecting a semiconductor integrated circuit from reverse engineering

A charge pump circuit that suppresses low boost efficiency is provided. The charge pump circuitof the invention includes a main pump circuit CPn_M and a gate controlling pump circuit CPn_G controlling the main pump circuit CPn_M. The main pump circuit has the same basic configuration as the controlling pump circuit, which are both KER-type pump circuits. The controlling pump circuit controls the operation of a transistor of the main pump circuit after the main pump circuit is boosted, so that reverse current will not flow from the main pump circuit to the forward section of the pump circuit.

Charge pump circuit, semiconductor device, and semiconductor memory device

A semiconductor memory device is provided. The semiconductor memory device includes a memory cell array, a read only memory (ROM), a central processing unit, and a random access memory (RAM). The memory cell array stores data related to operating conditions of the semiconductor memory device. The ROM stores data used to control an operation of the semiconductor memory device. The central processing unit controls the operation of the semiconductor memory device according to the data read from the ROM. The central processing unit reads the data related to the operating conditions from the memory cell array in response to a requested operation and then temporarily stores the read data related to the operating conditions in the RAM. The central processing unit further reads the data related to the data related to the operating conditions from the RAM for controlling the operation of the semiconductor memory device.

Semiconductor memory device and operation setting method thereof

A voltage generation circuit, having a circuit scale significantly reduced as compared with the related art, is provided. The voltage generation circuit of the disclosure includes a charge pump outputting a boosted voltage to an output node, a resistor connected between the output node and another output node, and a current source circuit having first and second current paths connected in parallel between the another output node and a reference potential. The first current path includes a resistor and a first DAC. The first DAC generates a first constant current corresponding to a voltage generation code. The second current path includes a second DAC. The second DAC generates a second constant current corresponding to a code obtained by inverting the voltage generation code. Thereby, a driving voltage obtained by lowering the boosted voltage is generated at the other output node.

Semiconductor memory device

A semiconductor memory device which is able to perform a power sequence with high reliability is provided. When a power from an external device is supplied, the controller of the flash memory of the invention is configured to read codes stored in a read-only memory in synchronization with a clock signal to perform a power-on sequence. In addition, the controller is further configured to deactivate the clock signal so as to pause the power-on sequence when it has been detected during the power-on sequence that the voltage of the power is not greater than a threshold, and to activate the clock signal to resume the power-on sequence when it is detected that the voltage of the supplied power exceeds the threshold again.

Semiconductor memory device and methods for operating a semiconductor memory device

A semiconductor storage device with a smaller chip size than prior art and a readout method are provided. The semiconductor storage device includes a memory cell array; a page buffer/sense circuit having a sensing node for sensing readout data from a selected page of the memory cell array and a latch circuit for holding data sensed by the sensing node; and a controller controls operations on the memory cell array. The sensing node includes an NMOS capacitor.

Semiconductor storage device and readout method thereof

A semiconductor memory device is provided. The semiconductor memory device includes a maintaining circuit, a sensing circuit, an output circuit, and a verification circuit. The maintaining circuit is configured to maintain data read from a memory cell array and output the data to a data bus in response to a column selection signal. The sensing circuit is configured to sense the data on the data bus in response to at least one sensing enable signal. The output circuit is configured to output the data sensed by the sensing circuit. The verification circuit is configured to verify an operation margin of the sensing circuit and output a verification result. The timing of the at least one sensing enable signal is set according to the verification result of the verification circuit.

Semiconductor memory device capable of correctly reading data

A semiconductor memory device which is capable of high-speed operation in synchronization with external control signals is provided. The semiconductor memory device has a data input portion, a memory array, a data output portion, and a control portion. The data input portion receives command and address input data in response to the external control signals. The memory array has a plurality of memory elements. The data output portion outputs data read from the memory array in response to the external control signals. The control portion has the function of delay-compensation. During the time interval for receiving the input data, the function of delay-compensation estimates the delay time of the internal circuits, stores the estimated delay-time in a memory unit, and adjusts the output timing of the data output portion.

A non-volatile semiconductor memory device and a driving method for word lines thereof are provided. A flash memory of the invention includes a memory cell array including blocks and a block selection element selecting the block of the memory cell array based on row address information and including a block selection transistor, a level shifter, a boost circuit and a voltage supplying element. The block selection transistor is connected to each word line of the block. The level shifter supplies a voltage to a node connected to a gate of the block selection transistor. The boost circuit boosts a potential of the node. The voltage supplying element supplies an operation voltage to one of the terminals of the block selection transistor. The node, after performing first boosting by the operating voltage supplied by the supplying element, performs second boosting by the second circuit.

Non-volatile semiconductor memory device and driving method for block selection by boosting thereof

A semiconductor device including a voltage generation circuit, and voltage generation circuit generates a required voltage according to internal data requested in response to an operation are provided. The voltage generating circuit includes a plurality of registers A-, B-, C-, D-, voltage generating blocks A-, B-, C-and a voltage switch. The registers A-, B-, C-, D-hold data provided from control logic. The voltage generating blocks A-, B-, C-generate voltage based on voltage control data held by the registers A-, B-, C-. The voltage switch selects voltages based on selection control data held by the register D-. The connecting element includes signal lines for sequentially transmitting the voltage control data or the selection control data, signal lines for sequentially transmitting a clock signal CLK and signal lines for controlling output of data held by the registers.

Semiconductor device including a voltage generation circuit, and voltage generation circuit generates a required voltage according to internal data requested in response to an operation

Provided is a flash memory device capable of restricting power consumption in an erase operation. The invention includes a plurality of wells, a power supply device, and a coupling device. The power supply device applies erase voltages to the wells for performing an erase operation. The coupling device performs selective coupling between the wells. When performing the erase operation on the wells, the power supply device applies the erase voltage to one of the wells, and applies the erase voltage to the other one of the wells after the coupling device electrically couples the one of the wells to the other one of the wells.

Flash memory device and erase method thereof capable of reducing power consumption

Growing community of inventors

Kanagawa, Japan

Hiroki Murakami