Panasonic Corporation

Matsushita Electric Industrial Co., Ltd.

Hiroki Mouri

Akira Yamamoto

Hiroyuki Nakahira

Kouji Okamoto

Hirokuni Fujiyama

Kouichi Nagano

Shiro Dosho

Takashi Yamamoto

Youichi Ogura

Yoshinori Shirakawa

Fumiaki Senoue

Hiroyuki Tezuka

A phase adjuster arranges phases of waveforms of a complex signal after orthogonal transform. An edge detector detects an edge of the complex signal after phase adjustment. A phase shift detector detects phase shift of an output signal of the edge detector between the in-phase signal and the quadrature signal after the orthogonal transform, and outputs a phase error signal (PE). The oscillator connected to mixers and a shifter to perform the orthogonal transform includes a phase adjustment section adjusting an edge of a voltage controlled oscillator (VCO) clock based on the phase error signal (PE) and correcting the phase shift of an original signal.

Orthogonal transform error corrector

In a digital PLL circuit, a phase comparison circuit counts the numbers of transitions of a reference clock and an oscillation clock, sets a time taken until the number of transitions of the reference clock reaches a reference count value as a phase comparison time period, and detects, as a phase error value, a difference between a target count value, obtained based on a magnification value of a desired oscillating frequency with respect to the frequency of the reference clock and the reference count value, and the number of transitions of the oscillation clock in the phase comparison time period. A smoothing circuit smoothes the phase error value. A digitally-controlled oscillation circuit controls the frequency of the oscillation clock in accordance with the phase error value smoothed by the smoothing circuit.

Digital PLL circuit, semiconductor integrated circuit, and display apparatus

An asynchronous timing detectordetects and measures a specific pattern (sync pattern) of audio and video reproduced signals having a digital value form an A/D converterand its appearance interval based on an asynchronous clock generated by an asynchronous clock generator, and calculates a cycle ratio of the measured sync pattern appearance interval (the number of clock pulses of the asynchronous clock) to a normal value (the number of clock pulses of a synchronous clock obtained by measuring a sync pattern appearance interval using the synchronous clock). A pseudo-synchronous clock generatorthins the asynchronous clock based on the cycle ratio to generate a pseudo-synchronous clock which is pseudo-synchronous with channel data. Therefore, even when an initial frequency error is large, frequency and phase pull-in is relatively quickly performed until a timing recovery operation becomes stable.

Timing extraction device and video display device

In a feedforward control type reproduced signal processor, a clock generatorchanges a clock frequency, depending on a digital value set by a digital value generator. Therefore, power consumption of a system is optimized and control is facilitated. Moreover, when a frequency lock state is established in which a frequency ratio calculated by a frequency ratio calculatorsatisfies a set condition, a modulation component having a small change is generated using a clock of a clock generator. Therefore, the digital value is updated with the modulation component, so that a change in clock frequency of the clock generatorgradually varies. As a result, the influence of the change in clock frequency on the response of a decoding process is reduced.

Reproduced signal processor and video display

A plurality of comparators (CMP, CMP, . . . ) respectively correspond to a plurality of reference voltages (V, V, . . . ), and each compares a reference voltage corresponding to the comparator with a signal level of an analog signal (Sin). An encoder () generates a digital signal (De) corresponding to the analog signal (Sin) based on outputs (S, S, . . . ) of the plurality of comparators. A pattern detection circuit () detects that a temporal change of an output (S) of a first comparator matches a predetermined first particular pattern. A control circuit () corrects a digital value of the digital signal (De) in response to detection by the pattern detection circuit. The temporal change of the output (S) of the first comparator becomes the first particular pattern when an amplitude of the analog signal (Sin) is smaller than a predetermined amplitude.

Analog-to-digital converter, optical disk reproduction device, and receiver device

In a feedforward timing extractor for extracting timing information from a playback signal, a frequency ratio calculation sectioncalculates the ratio between the frequency of the playback signal and the frequency of the output clock of a frequency synthesizerby utilizing a specific pattern and a specific pattern appearing interval in the playback signal. A control sectioncontrols the frequency dividing rate of the frequency synthesizerin such a manner that the frequency ratio calculated by the frequency ratio calculation sectionhas a set value. Thus, as compared with a case in which the output clock of the frequency synthesizeris a high-frequency fixed-rate clock, it is not necessary to operate the digital circuits at high speeds. Consequently, even in cases where the playback frequency (the playback rate) of the signal changes with time, the decimation rate at which pulses of a fixed clock are eliminated is constant, thereby reducing power consumption.

Timing extractor, and information playback apparatus and DVD device using the timing extractor

A write compensation circuit of a recording device includes a first delay portion driven by a first driving voltage, for receiving a clock signal, delaying the clock signal by a first delay time, and outputting the delayed clock signal, and a voltage supplying portion for supplying the first driving voltage to the first delay portion in such a manner that the first delay time is substantially equal to a clock period of the clock signal.

Write compensation circuit and signal interpolation circuit of recording device

The present invention is made to improve the conventional analog processing that is easily affected by variations in semiconductor processing. This invention provides a wobble signal processing apparatus that can reduce the circuit scale and the power consumption as well as improve the quality of signal processing. The wobble signal processing apparatus of the present invention digitally processes a part that has conventionally been processed by an analog system, and a PRML circuit is further provided to implement error detection, whereby the circuit scale and the power consumption is reduced. This improves the detection of a signal that is inputted to the wobble signal processing apparatus.

Wobble signal processing apparatus

The signal processor includes an analog filter, an analog-to-digital (A-D) converter, an adaptive equalization filter, a quality value calculating circuit, and a control circuit. The analog filter removes high-frequency noises of a played-back signal from a recording medium and amplifies a specific frequency band of the played-back signal. The A-D converter converts the played-back signal from the analog filter into a digital signal. The adaptive equalization filter performs waveform equalization of the played-back signal from the A-D converter while adjusting a tap coefficient of the adaptive equalization filter so as to reduce a difference between an output of the adaptive equalization filter and a target value. The quality value calculating circuit calculates a quality value based on the difference between the output of the adaptive equalization filter and the target value. The control circuit compares the quality value calculated by the quality value calculating circuit with a predetermined reference value, and conducts a process for improving the quality value according to the comparison result.

Signal processor

A waveform equalizer, which has a partial response characteristic represented in the form of PR (a, b, c, b, a) which is a quaternary transfer function characteristic, is made up an analog filter, an ADC (analog/digital converter), and an FIR filter, for providing matching with the frequency characteristic of a read back waveform read from a recording medium. Such signal processor characteristic approximation to the regenerative signal characteristic makes it possible to easily achieve equalization without particularly emphasizing the regenerative signal, thereby achieving a reduced circuit scale.

An encoding efficiency higher than 1 is achieved by accomplishing ternary recording on a recording medium. For this purpose, an 8-bit binary data word is converted to a 5-symbol ternary code word. A look-up table stores a modulation/demodulation table defining the correspondence between the binary data word ( B) and the ternary code word ( T). A table generating circuit generates the modulation/demodulation table to be stored in the look-up table such that each of constraints specified by a plurality of parameters is satisfied. If a PRML (Partial Response Maximum Likelihood) scheme is combined with an 8B5T code thus obtained, a signal-to-noise ratio is improved.

Multilevel record modulator and demodulator

An adaptive digital filter of the present invention includes: a pipelined filtering section for performing a filtering operation based on input data and coefficient data so as to output filtered data; and a non-pipelined adaptation section for outputting the coefficient data to the pipelined filtering section by performing a coefficient adaptation operation in a non-pipelined process based on the input data and the filtered data so that the filtered data output from the pipelined filtering section converges to a predetermined reference value.

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Osaka, Japan

Hiroki Mouri