Matsushita Electric Industrial Co., Ltd.

Hiroki Kojima

Hisashi Adachi

Shunsuke Hirano

Yasunori Miyahara

Yukio Hiraoka

Hisashi Takahashi

Ryoichi Yamada

A variable capacitor element including: a buried electrode layer of a conductivity type different from a semiconductor substrate; a wiring layer connected to the lead portion of the buried electrode layer; a pair of capacitive insulating films that are formed as regions having mutually opposing adjacent sides in a plane shape on a portion of the buried electrode layer excluding the lead portion; an insulator layer formed on the border region of each outside of the pair of capacitive insulating films in a direction perpendicular to the adjacent sides; a pair of conductor layers formed both on the respective capacitive insulating films and on the respective insulator layers; and wiring layers that are connected respectively to lead portions of the pair of conductor layers above the insulator layer. The capacitance value between the buried electrode layer and each of the conductor layers can be changed by changing the voltage between the buried electrode layer and the conductor layers. A parasitic capacitance between the respective variable capacitor elements is reduced.

Variable capacitor element and integrated circuit having variable capacitor element

A frequency synthesizer device comprising a PLL circuit ( ) and a frequency-division ratio control circuit ( ). The PLL circuit ( ) includes a phase comparator ( ), a low-pass filter ( ), a voltage-controlled oscillator ( ), and a variable frequency divider ( ). The frequency-division ratio control circuit ( ) controls the variable frequency divider ( ) such that a frequency division ratio of the variable frequency divider ( ) is changed in time and a time average value of the frequency division ratio contains a value below a decimal point. Two different signals of an output signal fdiv of the variable frequency divider ( ) and an output fdiv obtained via a delay element ( ) are used as clocks of an accumulator portion ( ) in the frequency-division ratio control circuit ( ). The variation in the substrate potential and the variation in the power supply voltage generated by the operation of the frequency-division ratio control circuit ( ) can be reduced, and the degradation of C/N of the frequency synthesizer can be suppressed.

Fractional-N frequency synthesizer with multiple clocks having different timings

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Otsu, Japan

Hiroki Kojima