Tohoku University

Hiroki Koike

Tetsuo Endoh

Hideo Ohno

Takahiro Hanyu

Shoji Ikeda

Takashi Ohsawa

Masanori Natsui

Akira Tamakoshi

Akira Mochizuki

A storage circuit includes a memory cell array of memory cells each including a variable resistance type element, a resistance-voltage conversion circuit RTto convert a resistance value of a memory cell MCto be read to a data voltage, a reference circuit and RTto generate a reference voltage, a sense amplifier to determine read data by receiving the data voltage and the reference voltage via first and second input terminals, respectively, and comparing both voltages with each other, and an analog buffer circuit arranged between the resistance-voltage conversion circuit RTand a first input terminal of the sense amplifier or between the reference circuit and RTand a second input terminal of the sense amplifier. Current driving capability of the analog buffer circuit is large.

Storage circuit provided with variable resistance type elements

A storage circuit includes: the array of a memory cell MC including a variable-resistance element; a conversion circuit that converts the resistance value of each memory cell into the signal level of an electric signal; a reference signal generation circuit that generates a reference signal common to a plurality of columns; a correction circuit that corrects one of the signal level of the reference signal and the signal level of the electric signal for each column of the array of the memory cell; and an RW circuit that determines data stored in the memory cell belonging to a corresponding column by comparing one of the reference level and the signal level of the electric signal, corrected by the correction circuit, and the other of the reference level and the signal level of the electric signal.

Storage circuit provided with variable resistance type elements, and its test device

A storage circuit () includes memory cells (MCij), each of which includes an MTJ element, and reference cells (RCi), each of which includes a series circuit of an MTJ element set to a low-resistance state and a linear resistor (FR). A RW circuit () that includes a sense amplifier is provided in each column of a memory cell array (), and compares a data voltage on a corresponding bit line (BLj) with a reference voltage. The sense amplifier includes a pair of PMOS transistors to which the data voltage and the reference voltage are applied, a CMOS sense latch that is connected to a current path of the PMOS transistors.

Storage circuit provided with variable resistance elements, reference voltage circuit and sense amplifier

An integrated circuit device of the invention, includes: a first resistance variable memory element provided on a semiconductor substrate; a second resistance variable memory element provided on the semiconductor substrate; and a semiconductor circuit for controlling write and read of the first resistance variable memory element and the second resistance variable memory element, which is provided on the semiconductor substrate, in which the second resistance variable memory element has a write current that is smaller than a write current of the first resistance variable memory element, and the second resistance variable memory element is disposed farther from the semiconductor substrate than the first resistance variable memory element.

Integrated circuit device

A circuit design support system, a circuit design support method, a circuit design support program, and a recording medium having the program recorded thereon are provided by which a design can be performed in consideration of the stochastic operation of the stochastic operation element and the influence caused by the stochastic operation of the stochastic operation element on the operation reliability of the circuit can be evaluated.

System, method, and non-transitory computer readable recording medium storing a program recorded thereon for supporting a design of a circuit including a stochastic operation element

A memory circuit () includes: a memory cell (MC) including a variable-resistance element in which a resistance value varies substantially between two levels; a resistance-voltage conversion circuit that converts the resistance value of a memory cell (MC) to be read into a data voltage; a reference circuit (RC) including a series circuit of a variable-resistance element and a linear resistor, the variable-resistance element including substantially the same configuration as the configuration of the variable-resistance element included in the memory cell MCand being set to a lower resistance of two levels; a reference voltage conversion circuit that converts the resistance value of the reference circuit (RC) into a reference voltage; and a sense amplifier (SA) that determines data stored in the memory cell (MC) by comparing the data voltage with the reference voltage.

Memory circuit provided with variable-resistance element

An integrated circuit that does not involve increase in power consumption or decrease in switching probability during a write operation that occur when a latch circuit using STT-MTJ device, etc. of the prior art is operated at high speed is provided. The integrated circuitincludes: a memory elementB where write occurs when a specified period &#x3c4; has elapsed after a write signal is input; and a basic circuit elementA, which is an elementary device constituting a circuit and has a data retaining function, and characterized in that an operation frequency fin a first operation mode in the process of memory access of the basic circuit elementA satisfies the following relation:&#x3c4;&#x3e;&#x3bb;(0&#x3c;&#x3bb;&#x2266;1).

Growing community of inventors

Sendai, Japan

Hiroki Koike