Nec Corporation

Nec Electronics Corporation

Other

Hitachi, Ltd.

Mitsubishi Electric Corporation

Sony Group Corporation

Elpida Memory, Inc.

Hiroki Koga

Naoki Kasai

Hiroshi Yoshida

Hiroshi Watanabe

Takuya Kitamura

Tetsuya Homma

Jun Okuno

Takaho Tanigawa

Mieko Suzuki

Yusuke Shuto

Kazutaka Taniguchi

Yukinobu Murao

Keisuke Fuchigami

The present disclosure relates to a semiconductor device enabling to suppress waste of energy consumption. There is provided a semiconductor device including: an input unit configured to input a charge; a memory unit configured to collect and accumulate a charge from the input unit; and an output unit configured to detect and output a charge accumulated in the memory unit. The memory unit includes a transfer unit to which a plurality of pairs of a gate unit and an accumulation unit is connected, the gate unit selects the accumulation unit that accumulates a charge, the transfer unit transfers a charge from the input unit to the accumulation unit selected by the gate unit, the accumulation unit accumulates a charge transferred from the transfer unit, and the transfer unit transfers a charge accumulated in the accumulation unit selected by the gate unit, to the output unit. The present disclosure can be applied to, for example, an analog memory device.

Semiconductor device

An input device () is connectable to a switch () to receive a state of the switch () input as a voltage corresponding to the state. The input device () includes an output circuit () to output a first voltage or a second voltage different from the first voltage, an input circuit () to receive the voltage input from the output circuit () via the switch () in a closed state and output input signals () corresponding to the input voltage, a diagnoser () to determine whether the input signals change in response to switching of the voltage from the output circuit () to the second voltage, and a generator () to generate a state signal () indicating the state of the switch () based on the input signals (). The second voltage differs from a reference voltage input to the input circuit () while the switch () is open.

Input device, and input diagnosing method

A semiconductor device has a pair of impurity regions in a semiconductor substrate. A silicon layer is formed on the impurity region. A gate insulating film is formed between the impurity regions. A gate electrode is formed on the gate insulating film. A first silicon nitride film is formed on the gate electrode. A silicon oxide film is formed on a side surface of the gate electrode. A second silicon nitride film is partially formed on the silicon layer and on a side surface of the silicon oxide film. A conductive layer is formed on the silicon layer.

Semiconductor device and method of manufacturing the same

A self-refresh control circuit includes a first constant current generating circuit that generates a constant current to change depending on the temperature, a second constant current generating circuit to generate a constant current not depending on the temperature, a current-cycle converting circuit selectively connected to the first constant current generating circuit and the second constant current generating circuit and converting the constant currents inputted from the first constant current generating circuit and the second constant current generating circuit into a test refresh cycle used for setting the refresh cycle.

Self-refresh control circuit for detecting current flowing from current generator and semiconductor device including same

Semiconductor device with double sidewall spacer and layered contact

A semiconductor device is disclosed including an IGFET (insulated gate field effect transistor) and a method of manufacturing the same. The semiconductor device may include an oxide film ( ) or a nitride film ( ) provided on a side surface of a gate electrode in such a manner that an overhang condition may not occur. In this way, operating characteristics of the IGFET may not be deteriorated and voids may not appear in filling regions of an interlayer insulating film so that isolation characteristics may not be deteriorated.

Semiconductor device including an insulated gate field effect transistor and method of manufacturing the same

In a non-volatile semiconductor memory device that has a floating gate that is formed on a semiconductor substrate with an intervening first gate insulation film, a second gate insulation film that is formed on the floating gate electrode, and a control gate that is provided over this second gate insulation film, at least two trenches are formed in the floating gate.

Method for manufacturing non-volatile semiconductor memory device

A semiconductor device, having a contact pad grown by an anisotropical silicon selective growth technique, includes a first word line crossing a diffusion layer formed on a substrate and surrounded by an element separating region at a right angle, a second word line parallel with the first word line formed over a rounded corner of the diffusion layer, and an area of the diffusion layer rectangularly partitioned by the first and second word lines. So that anisotropical silicon selective epitaxial growth from this area of the diffusion layer is achieved, avoiding isotropical growth deteriorated by the rounded corner.

Semiconductor device having a selectively-grown contact pad

An output buffer circuit is provided, which decreases a delay time of change of a digital output signal with respect to change of a digital input signal and which is capable of higher-speed switching operation. This output buffer circuit is comprised of a pair of a first p-channel MOSFET and a first n-channel MOSFET located in an output stage through which an output signal is derived; a first clamp circuit for clamping a gate voltage of the first p-channel MOSFET at a first clamp level for a first specific period, thereby increasing a rising rate of the output signal; and a second clamp circuit for clamping a gate voltage of the first n-channel MOSFET at a second clamp level for a second specific period, thereby increasing a falling rate of the output signal. A first resistor is connected to the first clamp circuit for suppressing a current flowing through the first clamp circuit. A second resistor is connected to the second clamp circuit for suppressing a current flowing through the second clamp circuit. A first capacitor is connected to the first clamp circuit for adjusting the gate voltage of the first p-channel MOSFET through its charging or discharging operation. A second capacitor is connected to the second clamp circuit for adjusting the gate voltage of the first n-channel MOSFET through its charging or discharging operation.

Output buffer circuit

A gate electrode,is provided on a surface of a semiconductor substrate,, an insulation film,being formed over the gate electrode,and the side wall of the gate electrode,being covered by an insulation film,, and, on a diffusion region,that is formed on the surface of the semiconductor substrate,at both sides of the above-noted gate electrode,and in a region that is sandwiched between the above-noted side walls,, a silicon single crystal is anisotropically grown in a direction that is perpendicular with respect to the semiconductor substrate,, so as to form a pad,, and the anisotropic growth of the silicon single crystal is only within a part,of the region sandwiched between parts of the side wall,that are perpendicular to the substrate surface.

Semiconductor device and method for manufacturing same

A semiconductor device includes a first diffusion layer, an insulating film, and an electrode. The first diffusion layer is formed on the surface of a first-conductivity-type semiconductor substrate and has an opposite conductivity type. The insulating film is formed on the first diffusion layer. The electrode is made of a conductor layer formed on the insulating film. The width of the electrode is smaller than a value twice the length by which an impurity doped into the surface of the semiconductor substrate, using the electrode as a mask, laterally diffuses during annealing to a position immediately below the electrode.

MOS semiconductor device and method of manufacturing the same

In order to provide a method for manufacturing a semiconductor device in which, in a trench isolation process of the semiconductor device, any void is not formed in trenches and a repeating pitch of the trench isolation can be reduced to the limitations of a lithography technique, the method of the present invention comprises, in the trench isolation process, a step of etching a silicon substrate through a hard mask to form trenches, and a step of processing the hard mask so that its upper portion may be tapered.

Method for manufacturing semiconductor device

In a 2.sup.m (m=1, 2, . . . )-valued semiconductor memory device, including a plurality of word lines, a plurality of bit line pairs, and a plurality of memory cells each connected to one of the word lines and one bit line of the bit line pairs, each of the bit line pairs are divided into m divided bit line pairs, and a ratio of capacitances of the m divided bit line pairs is 1:2: . . . :2.sup.m-1. Also, each sense amplifier is connected to one of the bit line pairs. Further, each of coupled capacitor pairs is cross-coupled between two adjacent divided bit line pairs of the divided bit line pairs.

Small-sized multi-valued semiconductor memory device with coupled

An insulation layer is formed on a silicon substrate. An SOI layer is formed on the insulation layer. A groove is selectively formed in the insulation layer. A bit line is buried in a lower half of the groove. A connection conductor layer is selectively formed on the side wall surface of the groove on the buried bit line. The SOI layer and the buried bit line are connected electrically via the connection conductor layer. A cap insulation layer is formed to fill the groove on the buried bit line in a region where said connection conductor layer is not formed.

Growing community of inventors

Tokyo, Japan

Hiroki Koga