Nihon Dempa Kogyo Co., Ltd.

Nihon Dempa Kogyo, Ltd.

Hiroki Kimura

Naoki Onishi

Yasuo Kitayama

Nobuo Tsukamoto

Tsukasa Kobata

Shoichi Tsuchiya

An oscillator includes an oscillator circuit, a crystal filter, a package portion, and a heating portion. The oscillator circuit is configured to output an oscillation signal. The crystal filter has a frequency characteristic where an attenuation at a detuned frequency is larger than an attenuation at an oscillation frequency of the oscillation signal. The detuned frequency is a frequency different from the oscillation frequency. The package portion covers a crystal blank of the oscillator circuit and a crystal blank of the crystal filter. The heating portion is configured to heat the crystal blank of the oscillator circuit and the crystal blank of the crystal filter using a resistor disposed between: a wiring board to which the package portion is secured, and the package portion.

Oscillator

A PLL circuit which can obtain a VCO output having satisfactory spurious output characteristics with respect to all channels and which can suppress the fluctuation of the characteristics due to a temperature change is disclosed. A control circuitprovides a frequency division ratio tablewhere frequency division ratios to improve spurious output characteristics in the output of a VCO for each channel number at temperatures are stored, and the control circuit reads, from the table, the frequency division ratio corresponding to the temperature detected by the temperature sensorand an input channel number, to set the frequency division ratio in a PLL ICand to set the channel number and the frequency division ratio in a DDS circuit. The DDS circuitcalculates the value of a reference frequency based on the channel number and the frequency division ratio to generate the reference frequency.

PLL circuit

Provided is a PLL circuit improving reliability while suppressing power consumption without degrading noise characteristics. The PLL circuit includes a PLL IC that divides an output frequency Fout from a VCO, compares phase with a reference signal, and feeds back a phase difference as a control voltage to the VCO. A control circuit is capable of finely setting both of a reference frequency Fref and an output frequency Fdds in a DDS circuit, and the DDS circuit generates folding signals of Fdds for Fref and an integral multiple frequency thereof based on the combination of the frequencies. A first AMP amplifies a signal, a variable filter selects a desired Fdds (desired) and a second AMP amplifies the signal and supplies the same to the PLL IC as a reference signal. The control circuit further supplies a division ratio N to the PLL IC.

There is provided an art to prevent an unstable operation due to temperature in a PLL apparatus in which a proper range of an amplitude level of an external reference frequency signal is specified and a control voltage is supplied to a voltage-controlled oscillator according to whether the amplitude level falls within the proper range or not. The PLL apparatus includes: a switching unit switching a signal that is to be supplied to a control voltage output unit between a signal of a phase comparison unit and a preset signal of a preset signal output unit; a protection circuit provided between a signal path of a reference frequency signal and a ground and having diodes that are connected in inverse parallel in order to regulate an amplitude level of the reference frequency signal; a temperature detection unit detecting an atmospheric temperature of the protection circuit; and a level detection unit detecting the amplitude level of the external reference frequency signal, and threshold values as references for the switching are set according to the detected temperature, thereby coping with a change in the amplitude level due to a temperature characteristic of the diodes.

PLL apparatus

To provide a highly stable oscillation frequency control circuit wherein the frequency thereof is corrected, an adequate range of the input levels of external reference signals is determined in accordance with temperature characteristics in detecting the external reference signal, and the control voltage to a VCO is controlled within and outside the adequate range. An oscillation frequency control circuit includes a selection switch that connects the phase comparator to the loop filter in an external reference synchronization mode and that connects the fixed voltage supplying circuit to the loop filter in a fixed voltage mode, and a CPU that switches the selection switch to the external reference synchronization mode or to the fixed voltage mode based on whether the detected voltage of an external reference signal level is within or outside of the adequate range.

Oscillation frequency control circuit

A VCO driving circuit and a frequency synthesizer wherein the impedance viewed from a VCO control terminal is reduced to prevent the VCO phase noise characteristic from degrading. A VCO driving circuit and a frequency synthesizer having the VCO driving circuit, which comprises a coarse adjustment DAC that receives a digital data, which has a coarse adjustment frequency, to output an analog signal; a fine adjustment DAC that receives a digital data, which has a fine adjustment frequency, to output an analog signal; a low response speed LPFthat removes noise from the output signal from the coarse adjustment DAC and then provides the resultant signal as an input to a VCO control terminal; a high response speed LPFthat converts the output signal from the fine adjustment DAC to a voltage, thereby smoothing the signal; a resistor that connects an input stage of the LPFto that of the LPF; and a capacitor used for providing a capacitive coupling such that the output of the LPFis added to that of the LPF

VCO driving circuit and frequency synthesizer

A PLL circuit which can absorb variation of phase noise characteristic due to temperature and individual difference and has a phase noise suppression characteristic stable in a wide frequency band is provided. The PLL circuit comprises, at the succeeding stage, a first register for storing a first parameter for controlling the loop gain, a first multiplier for multiplying the output of the phase comparator by a first parameter, a second register for storing a second parameter for controlling the response characteristic, a second multiplier for multiplying the output of the first multiplier by a second parameter, and a CPU for setting optimum parameters in the first and second registers depending on the use frequency band, the ambient temperature, and the device individual difference. By controlling the loop gain and the response characteristic to optimum values, a good suppression characteristic in a wide frequency band is achieved.

A digitally controlled PLL oscillation circuit has a VCO, a frequency divider, a reference oscillation circuit, an A/D converter, a phase comparator, a digital filter, a D/A converter, and an analog filter. A reference signal supplied from the reference oscillation circuit is output through a narrow-band crystal filter (MCF) to the A/D converter to cancel noise, jitter and a spurious wave included in the reference signal, making it possible to prevent the phase noise characteristic and spurious characteristic of a VCO output from being degraded.

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Chitose, Japan

Hiroki Kimura