Mitsubishi Denki Kabushiki Kaisha

Fuji Xerox Co., Ltd.

Renesas Technology Corp.

Renesas Electronics Corporation

Thine Electronics, Inc.

Ipflex Inc.

Konami Digital Entertainment Co., Ltd.

Hiroki Honda

Yoshiyuki Ishigaki

Masahiro Ishida

Kimiharu Uga

Yukio Maki

Masatoshi Kimura

Shigenobu Maeda

Takashi Ipposhi

Tomohisa Wada

Hirotoshi Sato

Hirotada Kuriyama

Rui Morimoto

Kotaro Yamada

Hajime Takahama

Kenta Noguchi

A transmission/reception systemincludes a transmission apparatusA, and a reception apparatusA. The transmission apparatusA includes a first switcha second switcha first transistora second transistora first differential amplifier, and a second differential amplifierThe reception apparatusA includes a first transistora second transistora first differential amplifiera second differential amplifiera first resistora second resistorand a reception unit

Transmission apparatus, reception apparatus, and transmission/reception system

There is provided a data processing apparatus () including a logic circuit () that is reconfigurable in each cycle and a library () that stores hardware control information (). The hardware control information () includes a plurality of pieces of cycle-based mapping information () for individually mapping a plurality of cycle-based circuits, which each realize a function in each cycle for executing an application, onto the logic circuit () and configuration selection information () for selecting at least one of the plurality of pieces of cycle-based mapping information according to an execution state of the application. The data processing apparatus () includes a control unit () that reconfigures at least part of the logic region () using at least one of the plurality of pieces of cycle-based mapping information () according to a request in each cycle based on the configuration selection information ().

Data processing apparatus including reconfiguarable logic circuit

Data processing apparatus including reconfigurable logic circuit

Provided is a computer system () including a storage () for storing a netlist (), and a contents generator () for generating a program () containing a statement to execute a plurality of operations of an operation portion contained in the netlist (). The operation portion includes an operation performing logic operations of multiple stages and having a plurality of inputs, and an operation of a previous stage for a plurality of input sources. The contents generator () includes an analyzer () for analyzing the operation portion from the output stage to the input stage and for judging that the operation of an object to be analyzed is such an operation when the plural inputs are partially determined that at least a portion of other inputs are don't care, and a converter () for reconstructing and outputting, if the judgment is YES, the statement to execute the operation of the analysis object into the statement to execute any of the operations of the plural input sources and to bypass the operation of the source of the input of the don't care.

Method for reconstructing statement, and computer system having the function therefor

There is provided a reconfigurable device that includes a plurality of processing blocks (), wherein operation logic of each processing block is changeable, and a routing matrix () for configuring paths that connect the plurality of the processing blocks. Each processing block () includes a logic operation unit () whose logic is determined by configuration data () and a storage unit () for storing processing results of the logic operation unit. Each storage unit () includes a plurality of storage elements (), input means () for selecting one of the plurality of storage elements () based on the configuration data () to store the output of the logic operation unit (), and output means () for connecting the plurality of storage elements () to the routing matrix ().

Reconfigurable device

There is provide a divided exposure technology capable of restraining deterioration in the performance of a solid-state image sensor. A photoresist is formed over a semiconductor substrate and subjected to divided exposure. A dividing line for divided exposure is located at least over a region of a semiconductor substrate in which an active region in which a pixel is to be formed is defined. The photoresist is then developed and patterned. By utilizing the patterned photoresist, an element isolation structure for defining the active region in the semiconductor substrate is formed in the semiconductor substrate.

Solid-state image sensor

A method using a divided exposure technology is provided for restraining deterioration in the performance of a solid-state image sensor. A photoresist is formed over a semiconductor substrate and subjected to divided exposure. A dividing line for divided exposure is located at least over a region of a semiconductor substrate in which an active region in which a pixel is to be formed is defined. The photoresist is then developed and patterned. By utilizing the patterned photoresist, an element isolation structure for defining the active region in the semiconductor substrate is formed in the semiconductor substrate.

Method for manufacturing solid-state image sensor

A channel region ( ), a source region ( ) and a drain region ( ) are formed on a polycrystalline semiconductor layer ( ). The characteristic of a polycrystalline TFT ( ) is dispersed by the amount of crystal grain boundaries ( ) contained in the channel region ( ). A drain current is reduced as the amount of the crystal grain boundaries ( ) contained in the channel region ( ) is increased. In order to utilize a code obtained by encoding the electric characteristic of the TFT ( ) for identification of a semiconductor chip, a system or the like, the TFT ( ) is mounted on the semiconductor chip, the system or the like along with an encoder circuit. Thus, a barrier against illegal use of a user terminal is improved at a low cost.

Semiconductor device, method of manufacturing semiconductor device and communication method

In a MOS semiconductor device including a normal MOS transistor and an output MOS transistor for an input/output buffer, the normal MOS transistor is formed in a normal well. In an output MOS transistor, the channel region of the second MOS transistor and an element isolation region are formed in the region of a higher impurity concentration. On the other hand, the source and drain regions are formed in a lower impurity concentration region. Thereby, the source/drain capacitance of the output MOS transistor may be reduced, and the input/output capacitance of the semiconductor device may be reduced.

Semiconductor device and method for fabricating the same

According to a semiconductor device and a method of manufacturing the same, a storage node has an increased capacity, and a resistance against soft error is improved. A GND interconnection is formed on a first interconnection layer including storage node portions with a dielectric film therebetween. Thereby, the storage node portions, the dielectric film, and the GND interconnection form a capacity element of the storage node portion. The first interconnection layer is arranged symmetrically around the center of the memory cell, and a plurality of memory cells having the same layout and neighboring to each other are arranged along the word lines.

Semiconductor device having memory cells and method of manufacturing the same

A semiconductor device including a shunt interconnection which operates at higher speed and permits high density integration is provided. In the semiconductor device including the shunt interconnection, a shunt connection region for a word line and a first shunt interconnection including a metal are formed in the memory cell region. In the memory cell region, shunt connection region and shunt interconnection are electrically connected with each other through a word line contact plug formed in a contact hole.

Semiconductor memory device including shunt interconnection

The capacitor includes a first electrode which has a hollow structure formed by removal of a nitride film and which is formed from a conductive layer, and a second electrode which is formed from a conductive layer on the outside surface of the first electrode and on the surface of the hollow structure, while an insulating film is sandwiched between the first electrode and the second electrode. The capacitor prevents a short circuit from arising between a capacitor electrode and a wiring pattern in the proximity of the capacitor electrode in an oxide film serving as an interlayer insulating film.

Semiconductor device having an improved capacitor structure, and a method of manufacturing the same

A layout structure of an SRAM for reductions in the number of interconnect layers and in the number of connection holes with conventional advantages maintained is disclosed. Contact holes and fields which have been shared between cells vertically adjacent to each other in plan view are divided between the cells. The cells are then positioned in translated relation also in a bit line direction (D1). In a resultant region, first-level polysilicon interconnect layers (1G(G)) for a GND line and first-level polysilicon interconnect layers (1G(W)) for a word line are formed in parallel in a word line direction (D2). Connection holes (GK2, GK1) for connecting gate electrodes of driver transistors (DTr1, DTr2) and fields (FL) are also used for connection holes (GK3) for connecting the fields (FL) and the GND interconnect layers (1G(G)). Further, interconnect layers having a high power supply potential is formed on the interconnect layers (1G(G)).

Layout structure of semiconductor memory with cells positioned in

A base region and an emitter region are formed at a surface of an n-well region (collector region). A contact hole reaching a portion of the surface of the collector region is formed, a contact hole reaching a portion of the surface of the emitter region is formed, and a contact hole reaching a portion of the surface of the base region is formed. A collector electrode, an emitter electrode and a base electrode are formed in the contact holes, respectively. Assuming that L represents a longitudinal length of the contact hole accommodating the emitter electrode and S represents a width thereof perpendicular to the longitudinal direction, a value of L/S is 10 or more. Thereby, a collector resistance of a bipolar transistor can be reduced, and a manufacturing cost can be reduced.

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Tokyo, Japan

Hiroki Honda