Nec Corporation

Nec Space Technologies, Ltd.

Itt Manufacturing Enterprises, Inc.

Nec Toshiba Space Systems, Ltd.

Nec Soft, Ltd.

Nec Toshiba Space System, Ltd.

Hiroki Hihara

Nobuyuki Kawai

Tadayuki Takahashi

Hiroaki Miyoshi

Eiichi Nakata

Takashi Kobayashi

Hideki Irisawa

Satoko Kawakami

Motohide Kokubun

Makoto Ohtsuka

Yasuhiko Mizushima

Yoshitaka Ishisaki

Yukikatsu Terada

Shuichi Moriyama

Masaharu Nomachi

Ryo Kameoka

Kazuyo Mizushima

Masanobu Ozaki

A basic logic element includes: a calculation unit configured to perform calculation processing; a self-diagnosis unit configured to self-diagnose whether or not there is an abnormality in a result of the calculation output from the basic logic element; a management unit configured to determine whether or not to retain authority to output the result of the calculation based on a result of the diagnosis performed by the self-diagnosis unit and output a result of the determination as an authority signal; and an output control unit configured to control whether or not to output the result of the calculation performed by the calculation unit based on whether or not the authority to output data is retained by the management unit.

Basic logic element, semiconductor device including the same, output control method for basic logic element, and non-transitory computer readable medium

In order to provide processor elements and programmable devices, which have little restriction on logical block arrangement and wiring, and which can improve a degree of integration, processor elementincludes: arithmetic unitsthat perform arithmetic processing on the basis of functions which have implemented instruction sets generated in accordance with programs; registersthat store arguments of the functions; bypass switchesof the arithmetic units; bypass switchesof the registers; a connection setting unitthat switches the connections of function units; a multiplexerthat switches the input to the connection setting unit; a demultiplexerthat switches the output destination of the output from the connection setting unit; and a selection unitthat switches, in accordance with a state, the bypass switches, the connection setting unit, the multiplexerand the demultiplexer

Processor element, programmable device, and processor element control method

An information record/reproduction apparatus includes logical volumes that can be used as a variable-length record/reproduction area and a physical volume that has been divided into a plurality of fixed-length areas and is not subjected to record or reproduction. Allocation to the logical volume is made by combining the divided fixed-length physical volumes by a management unit, and the size of the information storage area can be set depending upon, for example, a category of information to be recorded. If the amount of information of high priority exceeds a size of a predetermined logical volume corresponding to the information while no unused physical volume is available, then the management unit detaches part of a logical volume in which information of low priority has been recorded, allocates the detached part to the logical volume corresponding to the information, and thus records the exceeding amount of information.

Information record/reproduction apparatus and record/reproduction method

In a data/strobe encoding scheme circuit in which data and a strobe signal are transmitted through different lines, changes respectively in the data and the strobe signal are employed as clock signals for a latching operation, and the data is transmitted to a succeeding-stage circuit operating on a second clock signal. The circuit latches predetermined data by an FF circuit and passes a data pair including a signal indicating that the data has been latched and held therein as well as the latched data to the succeeding-stage circuit, activates, if assertion of a signal indicating reception of the data is received from the succeeding-stage circuit, again the FF circuit which has latched the data and has entered a stop state, and receives new data. There is provided a data/strobe encoding scheme circuit and a data/strobe encoding method, it is possible to implement a data/strobe encoding scheme circuit and a data/strobe encoding method capable of realizing a low-cost data/strobe encoding scheme which is independent of LSI device characteristics and which can be easily designed.

Data/strobe encoding scheme circuit and data/strobe encoding method

A connector includes a plurality of contacts. The connector includes an insulator having a plurality of through-holes for receiving the contacts. A pair of contacts are disposed in each of the through-holes. Since two contacts are disposed in the through-hole in the insulator, even if a fault occurs in one of the contacts, signal transmission in the same line can continuously be used. Moreover, since large areas of contact portions of the contacts are secured even in normal use, the capacity of electric current is increased.

Connector and contacts for use in the connector

A fault tolerant computer comprising plural operation controllers is provided, which can judge and separate a damaged element by using a double-redundant structure without using a triple or greater-redundant structure. The computer comprises two judgment sections corresponding to each operation controller in the double-redundant structure, and each judgment section compares an output from the operation controller connected to the present judgment section with an output from the operation controller connected to the other judgment section, wherein one judgment section receives a signal indicating a comparison result from the other judgment section, and collates this signal and a comparison result obtained in the present judgment section with reference to additional diagnosis information so as to judge whether the output from the operation controller connected to the present judgment section is correct.

Fault tolerant computer employing double-redundant structure

In each module (11) of three or more central processor modules of a fault tolerant computer system, a detector (45) receives a comparator output signal and like comparator output signals from two adjacent modules and produces a detector output signal which confirms absence and presence of a fault in one of the above-mentioned each module. When the fault is confirmed, a controller or processor (49) isolates the module under consideration from the system by inhibiting delivery of a controlled output signal to a bus (31) and by connecting, with the module in question bypassed, switching units (53(1), 53(2)) of the adjacent modules. Preferably, one of the modules of the system is used as a master module of ordinarily delivering the controlled output signal to the bus with others used as checker modules of ordinarily inhibiting the delivery. When a fault appears in the master module, its controller delivers a module operation switching signal to the controllers of the checker modules to thereby substitute one of the checker modules for the master module subjected to the fault.

Fault tolerant computer system comprising a fault detector in each

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Tokyo, Japan

Hiroki Hihara