Kabushiki Kaisha Toshiba

Hiroki Fujimura

Atsushi Kunimatsu

Toshiyuki Yaguchi

Hiroyuki Takai

Seiji Koino

Mikio Takasugi

Takashi Miyamora

An instruction code is received by an instruction input section 103 and then decoded by the instruction decode section 105 to generate an operand and control signals. The instruction division control section 109 generates a division control signal based on the control signals and an operand selection section 107 generates an operand having a desired bit width by using the operand from the instruction decode section 105 based on the division control signal. An arithmetic section 111 divides the operand into a desired bit width parts based on the division control signal and performs arithmetic operation. A memory access control section 115 receives calculated address and transfers this calculated address and the division control signal to a memory. The memory access control section 115 receives data from the memory and transfers the data into the arithmetic result store section 113.

Processor architecture with divisional signal in instruction decode for

A shift circuit consists of a sequence of a first stage shifter for receiving 32-bit input data, a second stage shifter, and a third stage shifter. The first stage shifter shifts the input data in a higher or lower direction by any one of 0 to 7 bits and provides the second stage shifter with a shifted 32-bit result. Each of the second and third stage shifters receives a shifted 32-bit result from the preceding stage shifter and shifts each byte of the shifted result independently in the higher or lower direction by 8 or 16 bits. The second and third stage shifters consist each of selectors that receive control signals, respectively, to realize various shifting operations on the input data, thereby providing a variety of data operations.

Shift circuit and system having the same

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Tokyo, Japan

Hiroki Fujimura