Sharp Kabushiki Kaisha Corporation

Hiroki Doi

Masanori Inamori

Toshiya Fujiyama

Tetsuya Akamatsu

Shigeyoshi Kitamura

Kenji Kaishita

Syouji Sakurai

There is provided a power-supply platform IC for realizing a parameter-deciding power-supply circuit, which, in order to decide a parameter of a power-supply circuit that supplies power to an electronic circuit IC (load), is connected to the electronic circuit IC (load) in place of the power-supply circuit. The power-supply platform IC includes: one or more transistor arrays that include a plurality of transistors operable as switching transistors; and a selecting circuit for selecting a transistor to be operated as a switching transistor from among the plurality of transistors, so as to control a size of the transistor that operates as a switching transistor, wherein the selecting circuit varies the size of the transistor as a parameter of the power-supply circuit, according to an external command.

Power-supply semiconductor integrated circuit, power-supply semiconductor integrated circuit system, development assisting system for power-supply circuit, and program and storage medium therefor

A charge pump DC/DC converter circuit of the present invention includes: a monitor circuit that detects a potential difference between terminals of a semiconductor switch that turns on during a first period, so as to output a determining signal corresponding to the potential difference; and each of drive circuits that outputs a drive signal to a semiconductor switch that turns on during a first period, in response to the determining signal. The drive signal increases the on-resistance of the semiconductor switch in proportion to the detected potential difference.

Charge pump DC/DC converter circuit

A power-on reset circuit comprises a power supply voltage detection circuit that detects a rise of a power supply voltage and that changes a logic level of a first internal node; a capacitor charge/discharge circuit that charges and discharges a capacitor according to the first internal node level and that in an event that the power supply voltage is reduced, discharges the capacitor to follow the event; and a reset pulse generation circuit that before the power supply voltage rises higher than the predetermined voltage, outputs a first output voltage to an output node and that after the power supply voltage has risen higher than the predetermined voltage, outputs a second output voltage to the output node upon detecting that a charge level of the capacitor has become higher than a charge level detection voltage.

Power-on reset circuit

In a negative voltage output charge pump circuit, first a capacitor C is charged with a positive voltage Vin relative to a reference voltage, and then the high-potential terminal A of the capacitor C is made to conduct to the reference voltage and simultaneously the low-potential terminal B of the capacitor C is made to conduct to an output terminal OUT so that the voltage with which the capacitor C is charged is output as a negative voltage &minus;Vin. Here, at least one of the switching device DP that is kept on while the capacitor C is being charged so as to apply the reference voltage to the point B and the switching device DP that is kept on while the negative voltage is being output so as to make the point B conduct to the output terminal OUT is a depletion-type transistor. This configuration makes it possible to realize a negative voltage output charge pump circuit that is free from malfunctioning caused by a parasitic device, that operates with low loss, and that can be produced at low costs.

Negative voltage output charge pump circuit

A Hall device biasing circuit includes a plurality of terminals for applying a bias voltage to a plurality of Hall devices connected in series, respectively. A magnetism detection circuit includes a plurality of Hall devices connected in series; and a Hall device biasing circuit including at least a plurality of terminals corresponding to the plurality of Hall devices for supplying a constant bias voltage to each of the plurality of Hall devices respectively from the plurality of terminals.

Hall device biasing circuit and magnetism detection circuit including the same

A delay circuit in accordance with the present invention includes: a first I L inverter and a second I L inverter connected in cascade with each other; and a capacitor interposed between a ground and a connecting point of the first and second inverters, wherein: the delay circuit further includes a current adjusting circuit having at least one third I L inverter with a plurality of output terminals at least one of which is connected to an input terminal of the third I L inverter; and the current adjusting circuit is connected to adjust a charge current of the capacitor. The configuration provides a delay circuit of simple circuit structure that accounts for a small area in an integrated circuit and that is capable of introducing any given delay and also provides a ring oscillator incorporating the delay circuit.

Delay circuit and ring oscillator incorporating the same

An IIL reset circuit includes an IIL inverter having input and output terminals, and a capacitor connected to the IIL inverter through the input terminal. When the IIL inverter is supplied with a constant current, it charges the capacitor through the input terminal, and outputs a reset pulse through the output terminal. The reset pulse has a pulse width that is determined based on both a current supplied to the capacitor, and on a capacitance of the capacitor.

Growing community of inventors

Tenri, Japan

Hiroki Doi