Seiko Instruments Inc

Gakkouhoujin Chikoujigakuen

Hirokazu Yoshizawa

Minoru Ariyama

Atsushi Igarashi

Toshiyuki Uchida

Ryoichi Anzai

Akira Takeda

Kenichi Kobayashi

Fumiyasu Utsunomiya

Masanao Hamaguchi

Provided is a chopper amplifier circuit capable of eliminating an influence of a slew rate of an amplifier and suppressing spike generation to thereby obtain an output signal having little harmonic distortion. The chopper amplifier circuit according to the present invention includes: a first chopper circuit for chopping an input signal by a first pulse and a second pulse shifted from each other in phase by a half cycle, switching a relation of connection between an input terminal pair and an output terminal pair at a timing of the chopping, and outputting the input signal as a modulated signal; an amplifier for amplifying the modulated signal and outputting the modulated signal thus amplified as an amplified signal; a first sample hold circuit for holding the amplified signal at the first pulse and outputting the amplified signal at the second pulse; and a second sample hold circuit for holding the amplified signal at the second pulse and outputting the amplified signal at the first pulse.

Amplifier circuit

Provided is a chopper amplifier circuit capable of reducing an offset voltage of a sensor bridge and temperature characteristics of the offset voltage. An offset adjusting voltage generation circuit for generating a voltage equal to an offset voltage of a sensor bridge and an offset temperature characteristics adjusting voltage generation circuit for generating a voltage having temperature characteristics equal to those of the offset voltage are provided. These output voltages are chopper-modulated and subtracted from a chopper-modulated output signal of the sensor bridge.

Chopper amplifier circuit and semiconductor device

A semiconductor device is provided, which includes a pair of differential transistors that convert a voltage difference between a first input terminal and a second input terminal into a drain current difference between a first transistor and a second transistor and in which a voltage range of the first input terminal or the second input terminal is wide. A SOI structure MOSFET is used as each of the pair of differential transistors. The MOSFET includes a general MOSFET structure including a source region, a drain region, a well region between both the regions, a gate oxide film on an upper surface of the well region, and a gate electrode on the gate oxide film, and further includes a first conductivity type substrate region under the source region, the drain region and the well region through a buried oxide film. In the MOSFET, the first conductivity type substrate region of the first transistor is the first input terminal, and the first conductivity type substrate region of the second transistor is the first input terminal.

Semiconductor device with transistors that convert a voltage difference into a drain current difference

An inverter circuit is disclosed that prevents flow of a large feedthrough current. The inverter circuit includes depletion type MOS transistor combined with a resistor to impose a current limitation when a feedthrough current flows.

Inverter circuit

In a pipeline A/D converter circuit, the time at which outputs of MDACs of the A/D converter circuit change is shifted at respective stages, so that a cumulative error is avoided. In a resistance ladder circuit for supplying reference voltages to sub-A/D converter circuits of the pipeline A/D converter circuit, main resistors and auxiliary resistors are alternately connected in series to prepare the reference voltages, and the reference voltage supplied to the first stage MDAC is made different from the reference voltage supplied to the second and subsequent stage MDACs. In an embodiment, the auxiliary resistors have a resistance value of no more than one-half that of the main resistors to provide the offset.

AD converter circuit

A reset circuit includes an invertor having one control input terminal to which a positive supply voltage and a potential lower than GND are supplied, and an n-channel transistor having a gate terminal connected to an output terminal of the invertor, a source terminal connected to a potential lower than the GND and a drain terminal connected to the GND.

Reset circuit

In a resistor ladder circuit for supplying reference voltages to sub-A/D converter circuits constituting a pipeline type A/D converter, the circuit is configured in such a way that main resistors are connected in series with auxiliary resistors in order to produce a plurality of reference voltages so that the reference voltages which are supplied to an MDAC in the first stage differ from those which are supplied to the MDACs in and after the second stage.

A/D converter circuit having ladder resistor network with alternating first and second resistors of different resistance values

A switched-capacitor amplifier circuit produces accurate output signal even if the input signal varies rapidly at every sampling phase. Two capacitors having the same capacitance are connected, in series with the input of an operational amplifier circuit. A switching circuit is connected between a first terminal and ground terminal. The two capacitors are connected with the first terminal.

Switched-capacitor amplifier circuit

There is provided a CR oscillating circuit from which oscillation frequency is obtained as targeted, when MOS capacitors having large voltage dependency are used therein. The circuit is constructed such that bias voltage is applied always to the two MOS capacitors by connecting the two MOS, capacitors in series in the opposite direction from each other and by connecting further a MOSFET.

Growing community of inventors

Chiba, Japan

Hirokazu Yoshizawa