Fujitsu Corporation

Fujitu Limited

Fujitsu Microelectroncis Limited

Hirokazu Yamazaki

Yasushi Kasa

Hisayoshi Watanabe

Sinsuke Kumakura

Hideaki Suzuki

Masanobu Yoshida

Kaoru Saigoh

Chikai Ono

Hisashi Miyazawa

Chikai Ohno

A reset circuit includes a power supply detection circuit, a power-down detection circuit, and an output circuit. The power supply detection circuit outputs a first signal when a first voltage according to a power supply voltage is higher than a first threshold and outputting a second signal when the first voltage is lower than the first threshold during power-on and power-down. The power-down detection circuit outputs a third signal when a second voltage according to the power supply voltage becomes lower than a second threshold after the second signal is outputted during power-down. The output circuit outputs a power-on reset signal which changes from low to high when the first signal is outputted during power-on and outputs a power-down reset signal which changes from low to high when the third signal is outputted during power-down.

Reset circuit

The semiconductor device having the capacitor comprises a plurality of switching elements formed on a semiconductor substrate at a distance, a plurality of capacitors formed in areas between a plurality of switching elements formed in the first direction respectively and each having a lower electrode, a dielectric film and an upper electrode, first wirings for connecting the upper electrodes of the capacitors and the switching elements in the first direction on a one-by-one base, and second wirings formed over a part of the first wirings, the switching elements, and the capacitors to extend in the second direction that intersects with the first direction. Accordingly, the higher speed operation than the prior art can be achieved.

Semiconductor device and method of manufacturing the same

A redundancy information region having memory cells for retaining relief information indicating the locations of defective memory cells is arranged closer to at least one of a word driver or a plate driver than a memory cell region and a redundancy memory cell region. Since the memory cells of the redundancy information region start operation earlier, a relief/no-relief judgment can be made earlier, allowing reduction in access time. Besides, in memory cell operations, the defective memory cells are deselected in accordance with address information held in a redundancy address region. Redundancy memory cells for relieving the defective memory cells are selected in accordance with the relief information held in a redundancy flag region. Since the redundancy memory cells are selected without using the address information, it is possible to reduce the time that elapses before the redundancy memory cells are selected after the selection of word lines.

Semiconductor memory

A ferroelectric memory includes memory cells, a pair of bit lines to which the memory cells are connected, and a control circuit which changes a reference cell applied to one of the pair of bit lines while data read from one of the memory cells is output to the other one of the pair of bit lines.

Ferroelectric memory and method of testing the same

Disclosed is an art making it possible that, in a reference cell circuit for outputting a plurality of different reference level signals, even if the number of transistors serving as reference cells and each having a floating gate increases, the time required for setting channel currents of the transistors will not increase. The floating gates of a plurality of transistors for generating different reference signal levels are connected in common so that the channel currents of all the transistors can be set simultaneously. The transistors have the channel lengths thereof, channel widths thereof, or both of them made different. The channel currents of the transistors are therefore mutually different. An error in all reference levels dependent on a manufacturing process is compensated for by adjusting an amount of charge to be injected into the floating gates.

Semiconductor integrated circuit for generating plurality of different

An object of the present invention is to provide a semiconductor device that permits easy and efficient testing. A nonvolatile semiconductor memory comprises word lines WLi and bit lines BLi, a memory cell matrix 17 consisting of nonvolatile memory cells Cij, a sense amplifier 15, a write/erase timing circuit 9 for performing timing control necessary for write and erase operations, and a status register 2 for storing the operating state of the memory at the completion of the operation of the circuit 9, wherein there are provided, outside the address of the memory cell matrix 17, two kinds of dummy cells, D1, D2, D3, . . . , whose values are fixed to different values that induce different outputs from the sense amplifier 15. A pass condition or a fail condition is generated by accessing the dummy cells.

Semiconductor memory having a sense amplifier with load transistors

An object of the present invention is to provided a semiconductor device that permits easy and efficient testing. A semiconductor device which is characterized in that the power supply for an output circuit is selectable between a normal power supply and an independent power supply provided independently of the normal supply.

Nonvolatile semiconductor memory device having a status register and

Semiconductor memory having non-volatile semiconductor memory cell

An object of the present invention is to provide a semiconductor device that permits easy and efficient testing. A nonvolatile semiconductor memory including word lines WLi and bit lines BLi, a memory cell matrix 17 including nonvolatile memory cells Cij, a sense amplifier 15, a write/erase timing circuit 9 for performing timing control necessary for write and erase operations, and a status register 2 for storing the operating state of the memory at the completion of the operation of the circuit 9, wherein there are provided, outside the address of the memory cell matrix 17, two kinds of dummy cells, D1, D2, D3, . . . , whose values are fixed to different values that induce different outputs from the sense amplifier 15. A pass condition or a fail condition is generated by accessing the dummy cells.

A semiconductor device for absorbing a noise comprises a first and second buffer. The first and second buffers receive an external signal having a rising edge and a falling edge, and performs waveform shaping thereof to produce an output signal. The first buffer, which issues an output signal for controlling the internal circuits of a chip of the semiconductor device so as to make the chip's internal circuits active/stand-by, is not sensitive to the rising edge of the external signal, but is sensitive to the falling edge of the same external signal. The second buffer, which issues an output signal for controlling an output circuit of a chip of the semiconductor device so as to make the output circuit active/stand-by, is sensitive to both the rising and the falling edges of the external signal.

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Kawasaki, Japan

Hirokazu Yamazaki