Fujitsu Corporation

Vlsi Technology Research Association

Hirokazu Suzuki

Takehiro Akiyama

Teruo Morita

Hirofumi Takeda

Masayuki Kokado

Kazumasa Nawata

Hikotaro Masunaga

A latch circuit inputting and holding a write data including a data input terminal for receiving a write data signal and a feedback input terminal for receiving a feedback signal from an output terminal, the latch circuit through a feedback loop, wherein the output terminal of the latch circuit outputs the write data signal at a suitable timing. The latch circuit is operated such that a potential difference between a peak voltage of a logic amplitude and a reference voltage at the side at which the feedback signal is applied is set larger than a potential difference between the peak voltage of the logic amplitude and the reference voltage at the side at which the write data signal is applied.

ECL latch circuit insensitive to alpha ray disturbances

A master-slice-type semiconductor integrated circuit device including basic cells, each having at least one logical circuit element, and current source cells for supplying current to the basic cells, each having at least one current source element and separated from the basic cells. A logic circuit operatively connects at least one logical circuit element in one of the basic cells and at least one current source element in one of the current source cells. The basic cells are arranged in groups extending in a lateral direction of the device and form cell rows in the lateral direction with groups of current source cells periodically formed in each cell row. The groups of current source cells in different cells rows are aligned in a longitudinal direction perpendicular to the lateral direction. The logic circuit is connected by conductive strips formed in wiring channels, each wiring channel being formed parallel and adjacent to at least one cell row.

Master-slice-type semiconductor integrated circuit device

A gate circuit device of an integrated circuit tester, for variably setting the signal propagation delay time of various integrated circuits to be tested at a predetermined value, includes a gate circuit having a pair of emitter coupled transistors and a constant current source transistor connected to the emitter side of the pair of transistors, and a terminal to apply a predetermined level of voltage to the base of the constant current source transistor to control the constant current. In addition to this manner of the voltage control of signal propagation delay time, a current adjustment circuit is utilized to generate current in a constant current source transistor in response to the control current. Thus, the gate circuit device controls the signal propagation delay time by regulating either voltage or current in response to the control current.

Variable delay gate circuit

An emitter coupled logic circuit includes a differential transistor pair and a set transistor, which are all emitter coupled. The logic level of the high voltage side of a set input signal to be applied, as a control input signal, to the set transistor is higher than the logic level of the high voltage side of the logic input signal pair to be applied, as control input signals, to the differential transistor pair. Simultaneously, the logic level of the low voltage side of the set input signal is lower than the logic level of the low voltage side of the logic input signal pair.

Emitter coupled logic circuit controlled by a set input signal

An ECL circuit includes a differential pair of transistors, a set transistor, and a set resistor connected between the emitters of the differential pair of transistors and the emitter of the set transistor. The output of the ECL circuit can be fixed securely to a 'high' level only by applying a 'high' level signal having the same level as the 'high' level signal of the data input to the base of the set transistor.

ECL Circuit for forcibly setting a high level output

A TTL circuit including an input circuit, an output circuit, elements for controlling the output circuit, and elements for delaying the operation of the controlling elements immediately after the voltage supply is turned on. The output of the TTL circuit is maintained at on 'H' level until the voltage supply rises up to a predetermined level.

TTL Circuit having delay means for delaying the operation until the

A semiconductor device is used, for example, for controlling and driving thermal heads of a facsimile apparatus and includes a first circuit activated when power is supplied to the semiconductor device and a second circuit activated only when both power and a power control signal are applied to the semiconductor device. The semiconductor device further includes a power switch circuit which includes a semiconductor electronic circuit and which supplies power to the second circuit only when the power control signal is applied thereto.

Semiconductor device for driving thermal print heads

A method of manufacturing a semiconductor device for simultaneously forming a plurality of diffused regions of selectively different diffusion depths, comprises forming polycrystalline semiconductor layers of corresponding, selectively different depths on the semiconductor substrate surface provided with a diffusion mask having a plurality of diffusion windows. By the impurity diffusion into the substrate through the windows at the polycrystalline semiconductor layer interface with the substrate, a comparatively shallow diffused region and a comparatively deep diffused region are formed simultaneously by a single diffusion process, respectively, under the comparatively thick polycrystalline semiconductor layer and the comparatively thin polycrystalline semiconductor layer.

Growing community of inventors

Yamato, Japan

Hirokazu Suzuki