Panasonic Corporation

Matsushita Electric Industrial Co., Ltd.

Komatsu Corporation

Hirokazu Sugimoto

Toru Iwata

Takashi Hirata

Hironori Akamatsu

Satoshi Takahashi

Yutaka Terada

Yoshihide Komatsu

Ryogo Yanagisawa

Akihide Namura

Yoshiaki Honma

Daisuke Tsukamoto

Hiroaki Tanaka

Koudou Tsuji

Tomoko Chiba

Tomoyuki Imada

Manabu Kawabata

A controller assembly includes a base plate, a bracket, and a first controller main body. The base plate includes a through hole and a frame having an upper surface and a lower surface and surrounding the through hole. The bracket has first and second flange portions supported on the upper surface of the frame at positions opposite to each other over the through hole, first and second side portions coupled respectively to the first and second flange portions and passing through the though hole; and a bottom portion coupled to both of the first and second side portions on the side of the lower surface of the frame. The first controller main body is mounted on a bottom portion of the bracket. Accordingly, a controller assembly which can be readily assembled, a cab of a work implement, and a work machine can be obtained.

Controller assembly, cab for work machine, and work machine

A driver supplies data signal via a supply node. A voltage-relaxing transistor has a source connected to the supply node of the driver, a drain connected to a signal node connected to a signal line, and a gate to which the voltage at the signal node is applied.

Data communication circuit, transmission apparatus, reception apparatus, and transmission/reception system

A cab for a construction machine includes hinges that swingably mount the door to the wall. Each of the hinges includes a first member secured to a first cut-out portion of the wall, a second member secured to a second cut-out portion of the door, an interposed member interposed between the first and second members, and first and second pivot shafts pivotally respectively coupling the first and second members to the interposed member. The cab further includes first and second stoppers that regulate first and second angles of the interposed member with respect to the first and second members, respectively, and a bolt member arranged in the second stopper to move in its axial direction to adjust the second angle. An imaginary surface corresponding to an outermost part of each of the hinges is substantially coplanar with exterior surfaces of the wall and the door, when the door is closed.

Cab for construction machine

A semiconductor integrated circuit (D) for receiving a parallel data signal and a first clock signal and outputting a serial data signal and a second clock signal, wherein a first clock generation circuit () produces a third clock signal obtained by multiplying the first clock signal by X/Y. A second clock generation circuit () has a variable transmission characteristic, and produces a fourth clock signal obtained by multiplying the third clock signal by N. A parallel/serial conversion section () converts the parallel data signal, which has been converted by a scaler (), to the serial data signal in synchronism with the fourth clock signal. A frequency divider () produces a fifth clock signal obtained by dividing a frequency of the fourth clock signal by N. A selector () selectively outputs, as the second clock signal, one of the third and fifth clock signals.

Semiconductor integrated circuit and transmitter apparatus having the same

The data receiver device includes: a bit phase synchronizing circuit () for performing phase adjustment of a received data signal to set a predetermined phase relationship between the data signal and a corresponding clock signal; and a state detection circuit () for outputting a detection signal once detecting that the data signal inputted into the bit phase synchronizing circuit () is in a stable state based on a data signal phase-adjusted by the bit phase synchronizing circuit () and a corresponding clock signal. The bit phase synchronizing circuit () initializes the phase adjustment of the data signal when receiving the detection signal.

Data receiver device and data transmission/reception system

In a signal receiving circuit there are provided N input detection circuitstofor receiving clock signals S-to SN-c included in N channels of signals Sto SN. Each of the input detection circuitstodetects the transition of the input signal of the corresponding channel and further confirms that the signal of the corresponding channel is being received after the transition detection to thereby detect the input of the signal of the corresponding channel. The selection circuitselects and outputs the clock signal and the data signal in the signal of the channel of which the input is detected. The selected output signal is successively subjected to input processes through one each of the phase synchronization circuit, the serial/parallel conversion circuit, etc., which are shared by N channels.

Signal receiving circuit and signal input detection circuit

A first semiconductor integrated circuit is connected to a second semiconductor integrated circuit with a cable. In the first semiconductor integrated circuit, when a power supply voltage becomes less than a set voltage detection level, a voltage-detecting circuit outputs a voltage-detected signal to lower the voltage of the cable and to stop the operation. The second semiconductor integrated circuit detects the decrease in the voltage of the cable to recognize the halt of the operation of the first semiconductor integrated circuit. In the first semiconductor integrated circuit thus configured, in testing the operation under low-voltage conditions in which the power supply voltage is less than the set voltage detection level, the voltage-detecting circuit receives a control signal from an external terminal to stop the operation forcibly. Consequently, even when the power supply voltage is made lower than the set voltage-detecting level, the first semiconductor integrated circuit properly operates until the power supply voltage reaches a predetermined lower limit of operating voltage. Thus, evaluation of operation is possible under low-voltage conditions.

Semiconductor integrated circuit with voltage-detecting circuit and signal transmitting and receiving system

A synchronization circuit includes a state detection circuit for outputting a control signal according to the temporal relationship between a transition point of an input signal and an edge of a synchronization clock, a delay selection circuit for adding a delay to the input signal based on the control signal, and a latch circuit for synchronizing the signal outputted from the delay selection circuit with the synchronization clock. Therefore, synchronization of the input signal can be carried out without adding latency to the input signal.

Synchronization circuit

In the circuit for detecting the voltage level of an analog signal, a conversion circuit converts an analog signal to digital signals by comparing the voltage level of the analog signal with a plurality of reference potentials. A filter circuit matches timings of at least either rising edges or falling edges of the digital signals with each other. This prevents malfunction in the voltage level detection.

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Osaka, Japan

Hirokazu Sugimoto