Sanyo Electric Co., Ltd.

Other

Hirokazu Ide

Haruhiko Murata

Hidefumi Okada

Yukio Mori

Akihiro Maenaka

Atsushi Kobayashi

Akio Kobayashi

Yasuhiko Naito

Tomio Ishigamii

A digital video camera includes an addition circuit in which an offset set by a CPU is added to an output from an A/D converter. A clamp level calculation circuit calculates a clamp level on the basis of an average level of eight pixels included in each line within a back end OB (optical black) level detection area in a normal mode, or calculates a clamp level on the basis of an average level of two pixels included in each line within a front end OB level detection area in a quadruplication mode. A first subtraction circuit subtracts the clamp level from an output of the addition circuit so as to clamp the output of the addition circuit. An output of the first subtraction circuit is clipped at a zero-level by a zero-clipping circuit, and an output of the zero-clipping circuit is applied to a second subtraction circuit through a low-pass filter, whereby the same offset can be subtracted from the output of the zero-clipping circuit.

Digital video camera with high-speed mode

An imaging device has a photosensitive array, a vertical transfer CCD array, a horizontal transfer CCD, a drain region, drain gates, a drive circuit and a processing circuit. An electric charge accumulated in the photosensitive array is first transferred to the vertical transfer CCD array, and then transferred from the vertical transfer CCD array to the horizontal transfer CCD. The electric charge held in the horizontal transfer CCD is transferred to the drain region at a predetermined timing defined by to a slow motion ratio N. The slow motion operation can be changed independently of the frequencies of the CCD drive signals. Therefore, the power consumption is much reduced and a slow motion ratio can be obtained.

Imaging device for recording and reproducing slow motion pictures

A signal processing circuit is utilized in a video camera which includes a CCD having pixels arranged in a dot-matrix fashion and color filters of R, G and B arranged in a mosaic fashion, and an output signal from the CCD is converted into a digital signal. A horizontal aperture signal (Hap) and a vertical aperture signal (Vap), which are produced on the basis of the digital signal, are multiplied by coefficients (K1, K2) which are obtained on the basis of a horizontal correlation value (Sh) and a vertical correlation value (Sv), and then, added to each other in an adding circuit, whereby an aperture signal is obtained by the adding circuit. The aperture signal is added to a luminance signal to perform an image enhancement.

Signal processing circuit for video camera which prevents a false

A color video camera includes a CCD, and digital signals of 4 lines produced on the basis of an outputs from the CCD are applied to a selection circuit which selectively outputs digital signals of 3 lines. A horizontal interpolation circuit and a vertical interpolation circuit perform interpolation calculation on the basis of the digital signals, and outputs a plurality of horizontal color signals and a plurality of vertical color signals, respectively. A horizontal correlation detection circuit and a vertical correlation detection circuit evaluate a horizontal correlation value and a vertical correlation value of a specific pixel with respect to pixels around the specific pixel. Horizontal and vertical weighing coefficients are calculated by a coefficient calculation circuit in accordance with the correlation values, and the coefficients are applied to a weighted addition circuit which adds the horizontal color signals and the vertical color signals to each other for each color in accordance with the coefficients, and outputs the color signals of the specific pixel.

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Osaka, Japan

Hirokazu Ide