Hitachi, Ltd.

Hitachi Engineering Co., Ltd.

Hirokazu Hirayama

Tadaaki Bandoh

Shinichiro Yamaguchi

Hidekazu Matsumoto

Kenji Hirose

Yoshihiro Miyazaki

Jushi Ide

Hiroaki Nakanishi

Soichi Takaya

Yukio Kawamoto

Kenichi Kurosawa

Masaru Shimada

Takayuki Morioka

Kiyomi Mori

Morioka Takayuki

High-speed inference method and system for a production system represented by an expert system. A knowledge base comprised of a rule and a fact possessing a plurality of attributes is converted into machine language instructions executable by a processor to execute inference. The machine language instruction of the fact has the function of transferring a value of the fact to a specified location and the machine language instruction of the rule has the function of performing matching decision by referring to the specified location. The number of pattern matching operations can be decreased and the interpretation overhead can be reduced to ensure high-speed inference.

Compile type knowledge processing tool, a high-speed inference method

Method and apparatus for instruction restart processing in a microprogram-controlled data processing apparatus, wherein, in restarting an instruction execution after instruction suspension, the internal information of the data processing apparatus at the time of instruction execution suspension is saved in a memory, and after a suspension cause removal process performed the saved internal information is recovered. A check point address associated with the address of a currently executing microprogram is stored in accordance with a designation by the microprogram. After a suspension causes removal process is performed, the execution of the instruction restarts using the check point address. If a check point address has not been stored after the suspension cause removal process is performed, the execution of the instruction restarts from a read operation of the suspended instruction from the main storage.

System for storing restart address of microprogram, determining the

Method and apparatus for instruction restart processing in a microprogram - controlled data processing apparatus, wherein, in restarting an instruction execution after instruction suspension, the internal information of the data processing apparatus at the time of instruction execution suspension is saved in a memory, and after a suspension cause removal process performed the saved internal information is recovered. A check point address associated with the address of a currently executing microprogram is stored in accordance with a designation by the microprogram. After a suspension causes removal process is performed, the execution of the instruction restarts using the check point address. If a check point address has not been stored after the suspension cause removal process is performed, the execution of the instruction restarts from a read operation of the suspended instruction from the main storage.

Suspended instruction restart processing system based on a checkpoint

An operation unit capable of performing round processing at a high speed in a floating point operation. A circuit for detecting an overflow on the condition of a signal representing all 1's in an output of a mantissa shifter and a signal representing round-up, a carry look-ahead circuit and a circuit for generating a round precision signal are provided. When the overflow takes place, the mantissa is produced as '1'. The operation unit is compatible to single, double and extended precisions recommended by Institute of Electrical and Electronic Engineers (IEEE).

Apparatus for performing floating point arithmetic operations and

A bit slice multiplication circuit operating to slice a multiplier, produce products for the sliced multipliers and a multiplicand and sum the products to obtain the multiplication result. The circuit includes a slicing unit for slicing the multiplicand, multiplying units corresponding in number to the number of sliced multiplicands, and adding units provided in correspondence to the multiplying units and implementing summation for multiplication results from corresponding multiplying units while shifting the sliced portions of the multiplicand at each multiplying operation for sliced multipliers and multiplicands by the multiplying units, the multiplication result being obtained by summing all summation results produced by the adding units.

Bit slice multiplication circuit

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Hitachi, Japan

Hirokazu Hirayama