Oki Electric Industry Co., Ltd.

Oki Semiconductor Co., Ltd.

Lapis Semiconductor Co., Ltd.

Hirokazu Hayashi

Yasuhiro Fukuda

Toshikazu Kuroda

Noriyuki Miura

Kouichi Fukuda

A junction forming region is formed between a drain region of a MOS structure and a device isolation region which surrounds the MOS structure and is in contact with the drain region, to form a PN junction together with the drain region. As a consequence, it is possible to adjust a breakdown voltage of an ESD protection device which is fabricated in the same process as that for an internal device without varying basic performance of the internal device even at a final stage of an LSI manufacturing process.

ESD protection device and manufacturing method thereof

According to a feature of the present invention, a semiconductor device includes a SOI substrate, including a semiconductor substrate; an insulating layer formed on the semiconductor substrate and a silicon layer formed on the insulating layer. A drain region and a source region are formed in the silicon layer so that the source region is in contact with the insulating layer but the drain region is not in contact with the insulating layer.

Semiconductor device using SOI-substrate

A semiconductor integrated circuit having an ESD protection circuit enhancing a durability against thermal destruction is provided. The semiconductor integrated circuit configured by a plurality of MOSFETs each having an SOI structure formed on a silicon substrate includes a functional circuit having an external connection signal terminal, a pair of power terminals and at least one of the MOSFETs. The semiconductor integrated circuit also includes at least one ESD protection circuit having a first terminal and a second terminal connected to the signal terminal and the power terminals, respectively. The ESD protection circuit includes at least one first MOSFET of the MOSFETs formed on the silicon substrate. The first MOSFET has a drain connected to the first terminal, a gate connected to the second terminal, and a source connected to the second terminal. The at least one ESD protection circuit also includes at least one second MOSFET of the MOSFETs formed adjacent to the first MOSFET on the silicon substrate. The second MOSFET has a gate connected to the first terminal and the same conductivity type as the first MOSFET.

Semiconductor integrated circuit

A load driving device includes a drive control signal generation circuit generating a load drive control signal and a semiconductor buffer circuit generating an output signal in response to the load drive control signal. The buffer circuit has a pair of gate driven switching elements which are connected to each other in push-pull configuration and driven at their gate terminals by the load drive control signal. The buffer circuit has an output terminal which is connected to a connection point between ends of controlled electrodes of the gate driven switching elements, and a power source terminal and a ground connection terminal respectively connected to the remaining ends of the other controlled electrodes of the gate driven switching elements. A ground connection side element of a pair of gate driven switching elements has a set of MOS transistors which are connected across the connection point and the ground connection terminal.

Load driving device

An electro-static discharge protection circuit and a semiconductor device having the same is disclosed. The electro-static discharge protection circuit has a current control circuit. The current control circuit has a first capacitive element. When the external source voltage is applied to the external source voltage supply line, the booster circuit in the internal circuitry boosts the internal source voltage of the internal source voltage supply line. The external source voltage becomes transiently greater than the internal source voltage at the early stage of the boosting step when the booster circuit boosts the internal source voltage based on the external source voltage. The first capacitive element restricts a current from flowing from the second terminal of the thyristor rectifier circuit to the internal source voltage, even when the external source voltage becomes transiently greater than the internal source voltage at the early stage of the boosting step when the booster circuit boosts the internal source voltage based on the external source voltage. This prevents the thyristor rectifier circuit from malfunctioning and turning on.

Electro-static discharge protection circuit and semiconductor device having the same

A semiconductor device includes a laminated substrate; a removal portion; a cavity; a first semiconductor element; and a second semiconductor element. In the laminated substrate, a bulk layer, an insulating layer, and a semiconductor layer are laminated in this order from a bottom. The laminated substrate includes a first area, a second area adjacent to the first area, and a third area adjacent to the second area in each of the layers. The semiconductor layer, the insulating layer, and an upper portion of the bulk layer in the first area are removed to form the removal portion. A part of the bulk layer in the second area is removed to form the cavity adjacent to the removal portion. The first semiconductor element is formed in the bulk layer in the removal portion as an ESD protection element. The second semiconductor element is formed partially in the semiconductor layer in the second area.

Semiconductor device having electrostatic discharge element

An electro-static discharge protection circuit includes a thyristor mode ensuring circuit and a thyristor rectifier circuit. The thyristor mode ensuring circuit includes a capacitive element connected between a higher potential line and a lower potential line, and ensures a constant and sufficient capacity independently of the number of input/output signal bits, even when the number of input/output signal bits is a theoretical minimum, i.e. 1, so that a surge current induced by electro-static discharge (ESD) applied to an output pad is injected into the first capacitive element to charge it. Thus, by means of the current caused by the surge current, the thyristor rectifier circuit is triggered into a thyristor mode, which allows the surge current to flow to the lower potential line through the thyristor rectifier circuit, protecting circuitry against the surge current.

An evaluation TEG for evaluating a semiconductor device including an SOI structure and a LOCOS having a birdbeak portion comprises two electrodesandhaving different electrode widths sufficiently large to disregard the length of the LOCOS birdbeak portion and an electrodehaving an extremely small width substantially equal to the length of the birdbeak portion. All the electrode have the same length and are connected to test padsa,a, anda, respectively. The capacitance of a parasitic transistor is easily extracted by using the evaluation TEG and the evaluation of parameters causing the hump characteristics is become possible.

Evaluation TEG for semiconductor device and method of evaluation

A physical analysis (S) of the elements used in an ESD protection circuit is performed; parameters of the elements that have a comparatively large effect on ESD protection characteristics are extracted as key parameters (S); and a mixed-mode device-circuit simulation of the ESD protection circuit is performed, using the key parameters, to optimize the key parameters (S). This can shorten the time required for designing an ESD circuit.

Design and simulation methods for electrostatic protection circuits

An ESD protection device modeling method of modeling an electrical characteristic of an electrostatic discharge (ESD) protection device for simulating a circuit that include the ESD protection device, comprising the steps of () setting a parameter of at least one specific element that affects the electrical characteristic of the ESD protection device; and () modeling the electrical characteristic of the ESD protection device with the parameter of the specific element.

Electrostatic discharge protection device modeling method and electrostatic discharge simulation method

The present invention provides a method of evaluating a semiconductor device having an ESD protective element, wherein a MOSFET is formed on the same substrate, comprising a step (electric characteristic measurement) for measuring an electric characteristic of the MOSFET, a step (snapback characteristic measurement) for measuring a snapback characteristic of the MOSFET, a step (impurity profile extraction) for extracting an impurity profile of the MOSFET from the electric characteristic and snapback characteristic of the MOSFET by using an inverse modeling technique, and a step (impurity profile adaptation) for causing the extracted impurity profile of the MOSFET and an impurity profile of the ESD protective element to correspond to each other, whereby the impurity profile of the ESD protective element is evaluated from the electric characteristic.

Method of evaluating semiconductor device

A method for using a computer to calculate a pileup state of an impurity in an interface between an Si layer in which a source and a drain are formed, and an SiOlayer brought in contact with the Si layer at a high speed, wherein data is first set assuming that the Si layer is constituted of a plurality of cells. Subsequently, the impurity is moved to a pileup position of the interface from each cell, and an amount of impurity piled up in each pileup position of the interface is calculated. In this case, a mass of the impurity moving to the interface from each cell is determined as a function of a distance to each pileup position from each cell, and a distance to a source or a drain closest to the cell.

Method for modeling semiconductor device process

An evaluation TEG for evaluating a semiconductor device including an SOI structure and a LOCOS having a birdbeak portion comprises two electrodesandhaving different electrode widths sufficiently large to disregard the length of the LOCOS birdbeak portion and an electrodehaving an extremely small width substantially equal to the length of the birdbeak portion. All the electrode have the same length and are connected to test pads, and, respectively. The capacitance of a parasitic transistor is easily extracted by using the evaluation TEG and the evaluation of parameters causing the hump characteristics is become possible.

A method for modeling a device and a network to be analyzed in a complex simulation. The modeling method includes a device extraction step for extracting the structure of each of a plurality of devices included in the network to create device models showing the individual extracted structures, a device connection step for connecting the respective device models through the intermediary of an insulating portion for cutting off the electrical connection between the respective device models, and a circuit connection step for connecting a network model showing the network portion, from which the plurality of devices extracted in the device extraction step have been excluded, to a predetermined device model among the connected device models.

Method for modeling semiconductor device and network

A semiconductor modeling method capable of simulating impurity pileup at a Si/SiO interface, and analyzing electrical characteristics (for example, substrate bias dependency) of a semiconductor, dependent on impurity concentration, under high speed calculation. A portion of impurities in a Si substrate region is caused to migrate to the Si/SiO interface, there by constituting an impurity pileup part. With such a method, it becomes possible to express the impurity pileups at the Si/SiO interface, which could not be expressed with the use of the conventional Fair model, without finding the solution to diffusion equations associated with point defects, that is without the use of the conventional pair diffusion model.

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Tokyo, Japan

Hirokazu Hayashi