Sanyo Electric Co., Ltd.

Semiconductor Components Industries, LLC

Sanyo Semiconductor Co., Ltd.

Kanto Sanyo Semiconductors Co., Ltd.

Hirokazu Fukuda

Noriaki Sakamoto

Yoshiyuki Kobayashi

Kouji Takahashi

Hiroki Etou

Hideyuki Inotsume

Shigeharu Yoshiba

Eiju Maehara

Junji Sakamoto

Katsumi Okawa

Shigeaki Mashimo

Haruhiko Sakai

Provided is a method for manufacturing a semiconductor device in which movement of an island in resin sealing is prevented. A molding die includes an upper die and a lower die. The upper and lower dies are fitted together to form cavities and runners. In the lower die, a pod is provided. After heating and melting of a tablet made of a solid resin and housed in the pod, the melted sealing resin is pressurized by a plunger, and is supplied to each of the cavities. Specifically, a liquid sealing resin is supplied from the pod to the cavities, sequentially, from the upstream of the flow of the sealing resin supplied from the pod. The cavities communicate with each other through the runners. Furthermore, the runners through which the cavities communicate are provided to be tilted with respect to a path for supplying the sealing resin.

Molding die with tilted runner, method of manufacturing semiconductor device using the same, and semiconductor device made by the method

A semiconductor device having a plurality of semiconductor chips mounted on lead frames is miniaturized by reducing its planar size and thickness. By disposing a rear surface of a first island and a top surface of a second island so as to at least partially overlap each other, a first semiconductor chip on the first island and a second semiconductor chip on a rear surface of the second island are configured so as to overlap each other. Accordingly, a planar occupied area can be set smaller than planar areas of both of the chips. Moreover, thin metal wires to be connected to the second semiconductor chip are extended to a back side. Consequently, a thickness of a semiconductor device can also be reduced.

Semiconductor device

By disposing a rear surface of a first islandand a top surface of a second islandso as to at least partially overlap each other, a first semiconductor chip on the first island and a second semiconductor chip on a rear surface of the second island are configured so as to overlap each other. Accordingly, a planar occupied area can be set smaller than planar areas of both of the chips. Moreover, thin metal wires to be connected to the second semiconductor chipare extended to a back side. Consequently, a thickness of a semiconductor device can also be reduced.

Semiconductor device with lead frames

A protection circuit device using a MOSFET has a plural of conductive paths separated electrically, a MOSFET chip integrating two power MOSFETs in one chip where a gate electrode and a source electrode are fixed on the desired conductive path, conductive material provided on a common drain electrode of the MOSFET, and insulating resin covering said MOSFET and supporting said conductive path in one body. Removing a drawing-around of the common drain electrode and fixing the source electrode directly on the conductive path, low ON-state resistance is realized.

Protection circuit device using MOSFETs and a method of manufacturing the same

A conventional one-chip dual MOSFET has a structure in which two chips are arranged side by side and drain electrodes are short-circuited. Therefore, the mounting area thereof is large, and the resistance between the drain electrodes cannot be reduced. Accordingly, there is a limit of reduction in size and thickness of a semiconductor device, which is demanded by the market. A dual MOSFET of the embodiment includes two semiconductor chips (MOSFET) superimposed on each other with drain electrodes thereof directly connected to each other. In the dual MOSFET, the drain electrodes do not need to be led to the outside, and only two gate terminals and two source terminals are used. Accordingly, these four terminals are led out by means of a lead frame or conductive patterns. This allows the device to be reduced in size and to have lower on-resistance.

Semiconductor device and switching element

Recently, there have been increasing demands for the reduction in size and weight of mobile computing/communication terminals as well as the elongation of the use time of the internal batteries. This invention alters the assembling structure of power MOSFET for reducing the on-state resistance and improving the production efficiency. This semiconductor device includes a lower frame having a header for fixing a semiconductor chip and corresponding external leads , a semiconductor chip fixed on the header, an upper frame having a connection electrode fixed on a current passage electrode formed on the top face of the semiconductor chip and the corresponding leads , and a resin mold . This two-frame configuration provides extremely low on-state resistance and good production efficiency.

Semiconductor device and manufacturing method thereof

After a trench is formed in a conductive foil , a circuit element is mounted in a flip chip method. Then, an insulating resin is covered on the conductive foil as a support substrate. After reversion, the conductive foil is polished over the insulating resin as a support substrate at this time to separate the conductive paths. Accordingly, a circuit device having the conductive paths and the circuit elements supported by the insulating resin can be produced without employing the support substrate.

Growing community of inventors

Gunma, Japan

Hirokazu Fukuda