Sony Corporation

Sony Semiconductor Solutions Corporation

Sony Group Corporation

Hirokazu Ejiri

Shigeru Kanematsu

Hiroyuki Miwa

Hiroaki Ammo

Takashi Noguchi

Takayuki Gomi

Akiko Honjo

Katsuyuki Kato

Hiroaki Anmo

Norikazu Ouchi

Hideki Mori

Koichi Baba

Kenji Azami

Terukazu Ohno

Nobuyuki Yoshitake

Taiichiro Watanabe

Masaaki Bairo

A solid-state image pickup apparatus according to a first aspect of the present technology includes a photoelectric conversion section that generates and holds a charge in response to incident light, a transfer section that includes a V-NW transistor (Vertical Nano Wire transistor) and transfers the charge held in the photoelectric conversion section, and an accumulation section that includes a wiring layer connected to a drain of the transfer section including the V-NW transistor and accumulates the charge transferred by the transfer section. The present technology is applicable to a CMOS image sensor, for example.

Solid-state image pickup apparatus and electronic equipment

A solid-state imaging device according to an embodiment of the present disclosure includes a mode-switching switch section that, in a first mode, electrically couples a first signal path to a photoelectric conversion section and electrically decouples a second signal path from the photoelectric conversion section, and that, in a second mode, electrically couples both of the first signal path and the second signal path to the photoelectric conversion section. At least the photoelectric conversion section is formed in a first substrate, and at least a second amplification transistor is formed in a second substrate, among the first substrate and the second substrate stacked on each other.

Solid-state imaging device and electronic apparatus including two floating diffusion regions

By stably separating a melting location of a fuse () from conductive layers (A,B), reliable melting of the fuse () is enabled. A fuse () including a fuse body (A) and two pads (Ba,Bb) connected by this and two conductive layers (A,B) individually connected to the two pads (Ba,Bb) are formed in a multilayer structure on a semiconductor substrate (). A length of the fuse body (A) is defined so that the melting location of the fuse () becomes positioned in the fuse body (A) away from the region overlapped on the conductive layer (A orB) when an electrical stress is applied between two conductive layers (A,B) and the fuse () is melted.

Semiconductor device

The present technology relates to a solid-state image pickup apparatus and electronic equipment that makes it possible to suppress read noise. A solid-state image pickup apparatus according to a first aspect of the present technology includes a photoelectric conversion section that generates and holds a charge in response to incident light, a transfer section that includes a V-NW transistor (Vertical Nano Wire transistor) and transfers the charge held in the photoelectric conversion section, and an accumulation section that includes a wiring layer connected to a drain of the transfer section including the V-NW transistor and accumulates the charge transferred by the transfer section. The present technology is applicable to a CMOS image sensor, for example.

A semiconductor device, an electronic apparatus, and a method of manufacturing a semiconductor device with reduced RTN influence regardless of gate electrode shape are disclosed. In one example, a semiconductor device includes a substrate having an element region and an element separating region, the element region including a source region and a drain region, and a channel region between the source and drain regions. The element separating region is arranged on both sides in a direction orthogonal to the source, channel and drain region arrangement direction. A gate insulating film is provided on the element region of the substrate from one side to another side of the element separating region. A gate electrode is provided on the gate insulating film, and includes an impurity having a different concentration in a boundary region as compared to a central region.

Semiconductor device, electronic apparatus, and method of manufacturing semiconductor device

The present disclosure relates to an information processing device, an information processing method, and a program that enable generation of stable PUFs. The information processing device includes: a reading unit that reads output data from a predetermined element a plurality of times; an average value calculation unit that calculates average values of the output data read by the reading unit; a median calculation unit that calculates the median of the average values calculated by the average value calculation unit; and a PUF generation unit that generates a physical unclonable function (PUF) by comparing the median with the average values. The predetermined element is an image sensor, and the reading unit reads output data from the image sensor when the image sensor is shielded from light. The present technology can be applied to imaging devices, for example.

Information processing device, information processing method, and program

Disclosed is a semiconductor device including a first semiconductor substrate and a first atom diffusion prevention portion, the first atom diffusion prevention portion being arranged at a part on the first semiconductor substrate and configured to prevent diffusion of an atom having a dangling bond terminating effect.

Semiconductor device with atom diffusion barrier layer and method of manufacturing semiconductor device with atom diffusion barrier layer

Disclosed is a semiconductor device in which the capacitive element of MIMC structure has a low parasitic capacity. A process for fabrication of said semiconductor device. The semiconductor device has a capacitive element of MIMC structure, a PN photodiode, and a vertical NPN bipolar transistor which are mounted together on the same semiconductor substrate. The lower wiring layer connected to the TiN lower electrode layer of the capacitive element of MIMC structure is formed on the insulating film and the first interlayer insulating film. Between this insulating film and the p-type semiconductor substrate is the p-type low-concentration semiconductor layer whose impurity concentration is lower than that of the p-type semiconductor substrate. This construction suppresses the parasitic capacity of the capacitive element of the MIMC structure. Thus, it is possible to realize a multi-functional high-performance integrated circuit in which the capacitive element of MIMC structure with a low parasitic capacity, the photodiode, and the bipolar transistor are mounted together on the same semiconductor substrate.

Semiconductor device and process for fabrication thereof

A semiconductor device for an integrated injection logic cell having a pnp bipolar transistor structure formed on a semiconductor substrate, wherein at least one layer of insulating films formed on a base region of the pnp bipolar transistor structure is comprised of a silicon nitride film. The semiconductor device of the present invention is advantageous in that the silicon nitride film constituting at least one layer of the insulating films formed on the base region of the pnp bipolar transistor prevents an occurrence of contamination on the surface of the base region, so that both the properties of the pnp bipolar transistor and the operation of the IIL cell can be stabilized. Further, by the process of the present invention, the above-mentioned excellent semiconductor device can be produced.

Semiconductor device for integrated injection logic cell and process for fabricating the same

Disclosed is a method for production of a semiconductor device having capacitive elements. The method includes steps of covering an insulating film formed on a substrate sequentially with a lower electrode film, a dielectric film, and an upper electrode film; applying a photoresist to the top of the films in laminate structure by photolithography, thereby forming a photoresist pattern to form an upper electrode; performing selective etching on the upper electrode film by using the photoresist pattern to form the upper electrode as a mask, thereby forming the upper electrode pattern; covering the upper electrode pattern with a photoresist pattern to form a dielectric pattern; and performing selective etching on the dielectric film by using the photoresist pattern to form the dielectric as a mask, thereby forming the dielectric pattern. The above-mentioned production method prevents a short circuit between the upper electrode and the lower electrode when the capacitive element is formed.

Method for protecting capacitive elements during production of a semiconductor device

Disclosed is a semiconductor device in which the capacitive element of MIMC structure has a low parasitic capacity. A process for fabrication of said semiconductor device. The semiconductor device has a capacitive element of MIMC structure, a PN photodiode, and a vertical NPN bipolar transistor which are mounted together on the same semiconductor substrate. The lower wiring layer connected to the TiN lower electrode layer of the capacitive element of MIMC structure is formed on the insulating film and the first interlayer insulating film. Between this insulating film and the p-type semiconductor substrate is the p -type low-concentration semiconductor layer whose impurity concentration is lower than that of the p-type semiconductor substrate. This construction suppresses the parasitic capacity of the capacitive element of the MIMC structure. Thus, it is possible to realize a multi-functional high-performance integrated circuit in which the capacitive element of MIMC structure with a low parasitic capacity, the photodiode, and the bipolar transistor are mounted together on the same semiconductor substrate.

Growing community of inventors

Kanagawa, Japan

Hirokazu Ejiri