Hitachi, Ltd.

Hitachi Vlsi Engineering Corp.

Other

Renesas Technology Corp.

Hitachi Ulsi Systems Co., Ltd.

Hitachi Microcomputer Engineering, Ltd.

Kogyo Gijutsuin

Hirokazu Aoki

Kunio Uchiyama

Takashi Toyooka

Mamoru Sugie

Osamu Nishii

Kanji Oishi

Susumu Hatano

Takashi Kikuchi

Yasuhiko Saigou

Hiroshi Fukuta

Koichiro Ishibashi

Hiroyuki Mizuno

Masayuki Miyazaki

Masaru Kokubo

Shigeru Yoshizawa

Kiyoshi Hasegawa

Norio Nakagawa

Katsuaki Takagi

Kazutoshi Yoshida

Shinsaku Chiba

Takeshi Sakata

Satoru Hanzawa

Katsuyuki Sato

Tadahiko Nishimukai

Yoshimune Hagiwara

Nobuo Saito

Kiwamu Takada

Ken Tatezawa

Ryo Suzuki

Kazuo Kato

Yutaka Sugita

Takashi Hotta

Susumu Narita

Kouki Noguchi

Fumio Arakawa

Takashi Sase

Shigeru Shimada

Kozaburo Kurita

Minoru Hiroshima

Kazuhiko Iwasaki

Atsushi Asano

Kazuhiro Ishida

Tatsuo Okahashi

Jun Kitano

Koichi Mayama

Kazuya Kamiyama

Yoshihiro Sekiguchi

A phase locked loop (PLL) circuit is provided to operate in a broad band, including two separate loops one of which is for feed-back of an output from an oscillator to the same oscillator through its associative proportional control unit and the other of which is for feed-back of an output of an oscillator to the same oscillator via an integral control unit. The proportional control unit is arranged to control an output frequency of the oscillator and is operable to generate a control signal based on a difference between input and output signals. The integral control unit is arranged to control the phase of an output signal of the oscillator to thereby generate a control signal based on a phase difference between input and output signals.

Phase-locked loop circuit, information processing apparatus, and information processing system

The oscillation circuit includes at least two ring oscillation circuits in each of which a plurality of inverters are connected in a ring shape in a multi-stage fashion, and a conductive wiring line. The output of at least one inverter of each of the ring oscillation circuits is connected to the conductive wiring line, whereby the plurality of ring oscillators are caused to oscillate at an identical frequency. A PLL is constructed in such a way that the oscillation circuit obtained by the above means is formed into a voltage-controlled oscillation circuit, and that a phase-frequency comparator, a charge pump circuit and a low-pass filter are employed.

Semiconductor integrated circuit having oscillators or oscillation circuits connected to a wiring line at connection points with intervals in length there between

A semiconductor integrated circuit device employing two clock signal generating circuits which output clock signals for distribution to an internal circuit of the device, the first and second clock signal generating circuits having different clock-settling times and the selection thereof is effected from outside of the device. A first one of the clock signal generating circuits uses, for example, a phase-locked loop circuit which has a large clock-settling time, and the second clock signal generating circuit is implemented, for example, using a delay-locked loop circuit whose clock-settling time is small, for example, 2-3 periods. Due to the selective actuation of the second clock signal generating circuit, which has a small clock-settling time, the generating of clock signals for the internal circuits can also be halted when the internal circuits of the device are halted thereby to further lower power consumption without compromising clock oscillator responsiveness.

Semiconductor integrated circuit device

An oscillation circuit provides clock signals and a clock distribution circuit or system of circuits having low skew and low jitter to logic circuits and memory circuits of a microprocessor or the like. Further, a semiconductor integrated circuit device of high speed is provided as a result of the stable clock signal that is generated and distributed. The oscillation circuit is in a semiconductor integrated circuit device having a plurality of oscillators each having an oscillation node, wherein the oscillation nodes of each of the oscillators are connected together by a conductive wiring line that may be a closed loop. The oscillators are synchronized to oscillate at substantially the same frequency. The oscillators are connected to the conductive wiring line at connecting points having substantially the same interval of conductive wiring lengths between the connection points, which leads to synchronizing the oscillators to oscillate with a substantially identical phase. The conductive wiring line can also be formed in the shape of a mesh with the interval of length of the conductive wiring line between the connection points being at least 50 &mgr;m. The oscillators are ring oscillation circuits having inverters connected in a ring shape wherein an output of at least one inverter of each ring oscillation circuit is connected to the conductive wiring. Alternatively, the oscillators may be delay lines having multistage connected inverters with at least one inverter connected to the conductive wiring line.

Semiconductor integrated circuit having oscillators or oscillation circuits connected to a wiring line at connection points with intervals in length therebetween

A signal from a crystal resonator or an external clock signal are input from terminals xta or exta and the signal from the crystal resonator or external clock signal are selected by mode terminal mod and input to an oscillator OSC. An input clock signal ckl is frequency-divided to desired values by a divider DIV A divided clock signal clk is input as the reference clock of a phase-locked loop PLL or delay-locked loop DLL and a clock signal output by a circuit selected by a selector SEL passes via a divider DIV to be distributed to an LSI. The phase-locked loop PLL has a clock settling time of at least 40 clock periods, whereas the clock settling time of the delay-locked loop DLL is 2-3 periods.

A timing-control circuit device, which uses a synchronous mirror delay circuit, for keeping the synchronization between clock signals in phase even at a load change. A reference clock signal (clkin ) is entered to a timing-control circuit (SMDF ) and used to generate an internal clock (dclk ), then generates an external clock (clkout ) through a buffer (BUF ). The external clock signal is fed back to the timing-control circuit (SMDF ) and used to generate an internal clock signal so as to synchronize the external clock signal in phase with the reference clock signal. The timing-control circuit is provided with a circuit (FDA , MCC ) for detecting a phase difference between the internal clock signal and the external clock signal, as well as a delay circuit (DCL ) for controlling a delay time, so that the delay circuit (DCL ) can change the delay time according to the detected phase difference.

Timing-control circuit device and clock distribution system

A timing-control circuit device, which uses a synchronous mirror delay circuit, for keeping the synchronization between clock signals in phase even at a load change. A reference clock signal (clkin,) is entered to a timing-control circuit (SMDF,) and used to generate an internal clock (dclk,), then generates an external clock (clkout,) through a buffer (BUF,). The external clock signal is fed back to the timing-control circuit (SMDF,) and used to generate an internal clock signal so as to synchronize the external clock signal in phase with the reference clock signal. The timing-control circuit is provided with a circuit (FDA,, MCC,) for detecting a phase difference between the internal clock signal and the external clock signal, as well as a delay circuit (DCL,) for controlling a delay time, so that the delay circuit (DCL,) can change the delay time according to the detected phase difference.

An address of a branch instruction, a branch target address thereof, and a type thereof are stored as branch history information in a branch instruction buffer. In addition, a return address for a return from a subroutine is retained in a return buffer. A look-up operation is conducted through the buffer by using the pre-fetch address such that when a hit occurs, a branch target address is output from the buffer depending on a branch instruction type. Consequently, the branch processing is achieved at a high speed. Particularly, the processing speed of an unconditional branch instruction containing a return instruction is increased.

Branching system for return from subroutine using target address in

A non-shared system with respect to an outside and an inside cache in a multi-processor system has multi-layer hierarchical cache. An invalidation address on a main memory address bus 31 in company with the rewriting of a main memory 30 is transmitted via a first and a second path 35, 36 to inside caches 11,21 so as to invalidate these inside caches 11, 21. The invalidation address is transmitted to the outside caches 12, 22 via the bidirectional connections between the main memory address bus 31 and outside caches 12, 22 so as to invalidate these outside caches 12, 22. It is extremely improbable for the address of access for writing to the transmitted to the main memory address bus 31 because the outside caches 12, 22 are operated in either copy back or write once system. As a result, even though the invalidation address is transmitted to the outside caches 12, 22 via the bidirectional connections between the main memory address bus 31 and the outside caches 12, 22, it is extremely improbably for the address of access for writing to conflict with a signal on the bidirectional connection.

Multi-processor system for invalidating hierarchical cache

Herein disclosed is a multiprocessor system which comprises first and second processors (1001 and 1002), first and second cache memories (100:#1 and #2), an address bus (123), a data bus (126), an invalidating signal line (PURGE:131) and a main memory (1004). The first and second cache memories are operated by the copy-back method. The state of the data of the first cache (100:#1) exists in one state selected from a group consisting of an invalid first state, a valid and non-updated second state and a valid and updated third state. The second cache (100:#2) is constructed like the first cache. When the write access of the first processor hits the first cache, the state of the data of the first cache is shifted from the second state to the third state, and the first cache outputs the address of the write hit and the invalidating signal to the address bus and the invalidating signal line, respectively. When the write access from the first processor misses the first cache, a data of one block is block-transferred from the main memory to the first cache, and the invalidating signal is outputted. After this, the first cache executes the write of the data in the transfer block. In case the first and second caches hold the data in the third state relating to the pertinent address when an address of an access request is fed to the address bus (123), the pertinent cache writes back the pertinent data in the main memory.

Multiprocessor cache system having three states for generating

A static memory cell is connected with word lines and data lines. First and second switches are connected in series between a data line and on output circuit. A sense amplifier has an input/output terminal connected to a common connection point of the said first and second switches. The first switch is turned off in synchronism with commencing operation of the sense amplifier such that the parasitic capacitance of the data line as viewed from the sense amplifier decreases. The second switching means is turned on a predetermined time later in order to transmit the output signal of the sense amplifier to the output circuit.

Static memory containing sense amp and sense amp switching circuit

In a cache memory setup, a buffer register is provided to accommodate the data read from a data memory. Between the buffer register and the data memory is connected a selector. This selector selectively transfers to the buffer register part of the data read from the data memory. The remaining part of the data is replaced with appropriate data for transfer to the buffer register. This arrangement provides the cache memory with a partial-write function.

Single-chip-cache-buffer for selectively writing write-back and

A static memory cell is connected with word lines and data lines. First and second switches are connected in series between a data line and an output circuit. A sense amplifier has an input/output terminal connected to a common connection point of the said first and second switches. The first switch is turned off in synchronism with commencing operation of the sense amplifier such that the parasitic capacitance of the data line as viewed from the sense amplifier decreases. The second switching means is turned on a predetermined time later in order to transmit the output signal of the sense amplifier to the output circuit.

Static memory containing sense AMP and sense AMP switching circuit

Single chip cache with partial-write circuit for transferring a

A main memory is subdivided into a shared region to undergo a write access from a plurality of processors and an input/output device and a plurality of private regions to undergo a write access only from the associated processor. Each of the cache devices includes a region discriminating circuit for determining whether an address generated from the processor is to be employed for an access to the shared region or to the private regions. If the access is to be conducted to the shared region, the cache devices operate according to the write-through method. On the other hand, if the access is to be conducted to the private region, the cache devices operate according to the copy-back method. When the processor or the input/output device rewrites data in the shared region of the main memory, the stored data of the shared region in the cache device of the processor is invalidated.

Multi-processing system and cache apparatus for use in the same

Growing community of inventors

Hachioji, Japan

Hirokazu Aoki