Mitsubishi Denki Kabushiki Kaisha

Renesas Electronics Corporation

Renesas Technology Corp.

Mitsubishi Denki Kabushiki Kasiha

Hiroji Ozaki

Shinichi Satoh

Takahisa Eimori

Wataru Wakamiya

Yoshinori Tanaka

Hiroshi Kimura

Masao Nagatomo

Shinichi Sato

Daisuke Okada

Tsutomu Okazaki

Motoi Ashida

Akira Tokui

Tsuyoshi Koga

Masayuki Nakajima

Akira Kawai

Masataka Minami

Hiroki Shimano

Yoshinori Okumura

Shigeki Obayashi

Ikuo Ogoh

Masahiro Yoneda

Takayuki Matsukawa

Atsuhiro Fujii

Shigeo Nagao

To provide a signal generation circuit having a short settling time of an output voltage. In a PTAT signal generation circuit, a trimming circuit is coupled between the cathodes of 0-th to K-th diodes and a line of a ground voltage, the anode of the 0-th diode is coupled to a first node, the anodes of the first to the K-th diodes are coupled to a second node via a resistive element, the first node and the second node are set to the same voltage, a first current flowing through the 0-th diode and a second current flowing through the first to the K-th diodes are set to have the same value, and a third current flowing through the trimming circuit is set to have the value 2 times that of each of the first current and the second current.

Signal generation circuit and temperature sensor

A manufacturing method of a semiconductor device includes a first electrode formation step of forming a control gate electrode above a surface of a semiconductor substrate with a control gate insulating film interposed between the control gate electrode and the semiconductor substrate, a step of forming a storage node insulating film on the surface of the semiconductor substrate, and a second electrode formation step of forming a memory gate electrode on a surface of the storage node insulating film. The second electrode formation step includes a step of forming a memory gate electrode layer on the surface of the storage node insulating film, a step of forming an auxiliary film, having an etching rate slower than that of the memory gate electrode layer, on a surface of the memory gate electrode layer, and a step of performing anisotropic etching on the memory gate electrode layer and the auxiliary film.

Semiconductor device having electrode and manufacturing method thereof

Semiconductor device having a split gate structure with a recessed top face electrode

A production management system has a plurality of pieces of production apparatus, a production controller connected online to the production apparatus, and a simulator. The simulator performs a simulation of physical distribution for a specified period of time through use of a simulation parameter, apparatus information, and process information, which are acquired from the production controller. A re-simulation of physical distribution is performed while taking, as parameters for optimizing physical distribution, time-series data pertaining to the availability factor of each apparatus and the load factor of each apparatus obtained as a result of the simulation, as well as the start and termination times of an event which is to arise in the period of a simulation. A dispatch rule set for each apparatus or a group of pieces of apparatus having a single function is dynamically changed, thus feeding back the change to control of real physical distribution.

Production management system

A manufacturing system compares information of foreign matter sensed by semiconductor equipment from on a semiconductor substrate with a selection reference thereby selecting optimum semiconductor equipment corresponding to the information of the foreign matter from a plurality of semiconductor equipment and processing the semiconductor substrate. Thus, a method of manufacturing a semiconductor device capable of improving the yield of the semiconductor device as well as a manufacturing system and semiconductor equipment to which the manufacturing method is applied, and a semiconductor device manufactured by the same are obtained.

Method of manufacturing semiconductor device, semiconductor equipment and manufacturing system

In order to solve various problems of a wafer, two-dimensional analysis using a wafer map is aided. An image of the wafer map is classified and displayed on a screen for each item such as a manufacturing step, a device and inspection. A trend chart is also attached in addition to the image of the wafer map.

Wafer map analysis aid system, wafer map analyzing method and wafer

Measurement result data obtained by the devices (A1 to A8) are stored in databases (C1 to C8). Every time new data are entered in any of the databases (C1 to C8), a database monitoring computer (E1) retrieves data related to the entered data from the data stored in the databases (C1 to C8) and stores the retrieved data in a failure analysis database (D3). A data analysis system (D0) gives a readout from the failure analysis database (D3) to an operator. The operator can thereby judge that some nonconforming defect is found and what the cause of nonconforming defect is even while the product wafer is on a fabrication line, to make a prompt remedy against the cause of nonconforming defect. Thus, a method and an apparatus for analyzing a fabrication line can be provided, allowing a prompt remedy against the cause of nonconforming defect.

Method and apparatus for analyzing a fabrication line

A first conductor for a field shield and a first insulating film are sequentially formed in a predetermined shape on a major surface of a P-type semiconductor substrate through an insulating film. A third insulating film is formed over the semiconductor substrate so as to cover the first conductor and a second insulating film thereon. The third insulating film is anisotropically etched, so that a sidewall insulating film is formed on sidewalls of the first conductor. Second and third conductors respectively serving as gate electrodes of field effect transistors are formed through a fourth insulating film. n-type impurities are implanted into the major surface of the semiconductor substrate utilizing as masks the first insulating film, the sidewall oxide film, the second conductor and the third conductor and are diffused, to form impurity regions. Since the sidewall oxide film is thick, the impurity regions are not overlapped even by diffusion with a portion where the first conductor is projected on the semiconductor substrate. Thus, a threshold voltage of a field shield transistor comprising the first conductor and the impurity regions on both sides thereof is raised, so that isolation characteristics of the field shield is improved.

Method for forming MOS device having field shield isolation

A field effect transistor comprises a semiconductor substrate having a main surface and a predetermined impurity concentration of a first conductivity type, impurity layers of a second conductivity type formed spaced apart at the main surface of the semiconductor substrate, and a shaped conductive layer serving as a gate electrode. The impurity layers constitute source.multidot.drain regions, and a region between the impurity layers defines a channel region in the main surface. The shaped conductive layer is formed on the channel region with an insulating film therebetween. The shaped conductive layer has an upper portion and a lower portion wherein the upper portion is longer than the lower portion and the length of the lower portion adjacent the insulating film is substantially equal to or shorter than the length of the channel region at the main surface. Additionally, the upper and lower portions of the shaped conductive layer are formed of the same base composition.

Field effect transistor with a shaped gate electrode

A field effect transistor comprises a semiconductor substrate having a main surface and a predetermined impurity concentration of a first conductivity type, impurity layers of a second conductivity type formed spaced apart at the main surface of the semiconductor substrate, and a shaped conductive layer serving as a gate electrode. The impurity layers constitute source.drain regions, and a region between the impurity layers defines a channel region in the main surface. The shaped conductive layer is formed on the channel region with an insulating film therebetween. The shaped conductive layer has an upper portion and a lower portion wherein the upper portion is longer than the lower portion and the length of the lower portion adjacent the insulating film is substantially equal to or shorter than the length of the channel region at the main surface. Additionally, the upper and lower portions of the shaped conductive layer are formed of the same base composition.

Method of making a field effect transistor with a T shaped polysilicon

A field shield isolating structure forms a structure for isolating elements of a semiconductor device. The field shield isolating structure includes a field shield gate insulating film and field shield electrode formed on the semiconductor substrate in separate processes to constitute a quasi-MOS transistor using impurity regions of adjacent MOS transistors. The film thickness of the field shield gate insulating film is set arbitrarily, the threshold voltage of the quasi-MOS transistor is set high, and then elements are insulated and isolated, so that the transistor is operated in the off state. The upper surface of the field shield electrode is also covered with the upper insulating film. The thicknesses of the upper insulating film and of the field shield gate insulating film is adjusted to have such values that prevent turning ON of the MOS transistor by the capacitance divided voltage. The voltage may be applied from upper conductive layers such as word lines formed above the upper insulating film.

Growing community of inventors

Hyogo, Japan

Hiroji Ozaki