Renesas Electronics Corporation

Renesas Technology Corp.

Hiroi Oka

Yuichi Yato

Takuya Nakajo

Hidemasa Kagii

Hiroyuki Nakamura

Osamu Ikeda

Tadatoshi Danno

Ichio Shimizu

Akira Muto

Atsushi Nishikizawa

Hiroshi Sato

Keiichi Okawa

Katsuo Arai

Keita Takada

Kazutoshi Itou

Noriko Okunishi

Masahiko Osaka

Takahiro Kainuma

Takamitsu Yoshihara

Toshiyuki Hata

Ryoichi Kajiwara

Masahide Okamoto

Kazunori Hasegawa

Kuniharu Muto

Ryouichi Kajiwara

Masatoshi Sugiura

Provided is a method of manufacturing a semiconductor device with improved manufacturing efficiency for the semiconductor device. The method of manufacturing a semiconductor device includes the steps of: (a) forming a circuit at a front surface side of a wafer (semiconductor wafer) having the front surface and a back surface opposite to the front surface; (b) grinding the back surface of the wafer that has a center part (first part) and a peripheral edge part (second part) surrounding a periphery of the center part in such a manner that the center part is thinner than the peripheral edge part; (c) attaching an upper surface (bonding surface) of a holding tape to the front surface of the wafer; and (d) separating the center part from the peripheral edge part by cutting a part of the center part with a blade (rotary blade) while the wafer is held by the first tape.

Method for manufacturing semiconductor device

A die bonding process for assembling a semiconductor device includes the steps of applying a sintered-silver-use paste to each of a plurality of first regions on an upper surface of a chip mounting part, drying the sintered-silver-use paste and applying a silver paste to a second region located between/among the respective first regions. Further, the process includes the step of mounting a semiconductor chip onto the chip mounting part in such a manner that a rear surface of the semiconductor chip faces an upper surface of the chip mounting part with the sintered-silver-use paste and the silver paste being interposed. After mounting the chip, part of each of first, second, third and fourth corners of a principal surface of the semiconductor chip is located in each of the first regions.

Manufacturing method for semiconductor device and semiconductor device

In a resin sealing type semiconductor device, a semiconductor chip CPis mounted over a die pad DP having conductivity via a bonding member BDhaving insulation property, and a semiconductor chip CPis mounted over the die pad DP via a bonding member BDhaving conductivity. A first length of a portion, in a first side formed by an intersection of a first side surface and a second side surface of the semiconductor chip CP, covered with the bonding member BDis larger than a second length of a portion, in a second side formed by an intersection of a third side surface and a fourth side surface of the semiconductor chip CP, covered with the bonding member BD

Semiconductor device and method of manufacturing the same

Reliability of a semiconductor device is improved. For this, embodied is a basic idea that a semiconductor chip (CHP) mounted on an Ag layer (AGL) is fixed by using a temporarily fixing material (TA) having tackiness without forming the temporarily fixing material (TA) on a surface of the Ag layer (AGL) having a porous structure as much as possible, is realized. More specifically, the temporarily fixing material (TA) is supplied so as to have a portion made in contact with a chip mounting part (TAB), and the semiconductor chip (CHP) is also mounted on the Ag layer (AGL) so that one portion of a rear surface of the semiconductor chip (CHP) is made in contact with the temporarily fixing material (TA).

Semiconductor device and manufacturing method thereof

A semiconductor device according to an embodiment is a semiconductor device in which a semiconductor chip mounted on a chip mounting part is sealed by resin and a first member is fixed to a chip mounting surface side between a peripheral portion of the semiconductor chip and a peripheral portion of the chip mounting part. Also, the first member is sealed by the resin. Also, a length of the first part of the chip mounting part in the first direction is larger than a length of the semiconductor chip in the first direction, in a plan view.

Semiconductor device

A die bonding portion is metallically bonded by well-conductive Cu metal powders with a maximum particle diameter of about 15 &#x3bc;m to 200 &#x3bc;m and adhesive layers of Ag, and minute holes are evenly dispersed in a joint layer. With this structure, the reflow resistance of about 260&#xb0; C. and reliability under thermal cycle test can be ensured without using lead.

Semiconductor apparatus, manufacturing method of semiconductor apparatus, and joint material

The present invention enables improvement of bonding reliability of the conductive adhesive interposed between a semiconductor chip and a die pad portion. Provided is a semiconductor device, in which a silicon chip is mounted over the die pad portion integrally formed with a drain lead, has a source pad over the main surface and a drain electrode of a power MOSFET over the back side, and is bonded onto the die pad portion via an Ag paste. In the device, a source lead and the source pad are electrically coupled via an Al ribbon. Over the back surface of the silicon chip, an Ag nanoparticle coated film is formed, while another Ag nanoparticle coated film is formed over the die pad portion and lead (drain lead and source lead).

Semiconductor device and manufacturing method of the same

To actualize a reduction in the on-resistance of a small surface mounted package having a power MOSFET sealed therein. A silicon chip is mounted on a die pad portion integrated with leads configuring a drain lead. The silicon chip has, on the main surface thereof, a source pad and a gate pad. The backside of the silicon chip configures a drain of a power MOSFET and bonded to the upper surface of a die pad portion via an Ag paste. A lead configuring a source lead is electrically coupled to the source pad via an Al ribbon, while a lead configuring a gate lead is electrically coupled to the gate pad via an Au wire.

In a power semiconductor device, a joint between the power semiconductor element and frame plated with Ni is composed of a laminated structure comprising, from the power semiconductor element side, an intermetallic compound layer having a melting point of 260&#xb0; C. or higher, a Cu layer, a metal layer having a melting point of 260&#xb0; C. or higher, a Cu layer and an intermetallic layer having a melting point of 260&#xb0; C. or higher. The structure of the joint buffers the stress generated by the secondary mounting and temperature cycle at the bond for the semiconductor element and the frame having a large difference in thermal expansion coefficient from each other.

Semiconductor device and method for manufacturing thereof

Pb free solder is used in die bonding. A thermal stress reduction plate is disposed between a semiconductor chip and a die pad made of a Cu alloy. The semiconductor chip and the thermal stress reduction plate are joined and the thermal stress reduction plate and the die pad are joined by a joint material of Pb free solder having Sn&#x2014;Sb&#x2014;Ag&#x2014;Cu as its main constituent elements and having a solidus temperature not lower than 270&#xb0; C. and a liquidus temperature not higher than 400&#xb0; C. Thus, die bonding can be performed using the Pb free solder without generating any chip crack.

Semiconductor apparatus and manufacturing method

A semiconductor chip is sealed by resin without covering an outer terminal of a semiconductor device having a power transistor. A semiconductor chip having a power transistor is housed within a recess of a metal cap while a drain electrode on a first surface of the semiconductor chip is bonded to a bottom of the recess via a connection material. A gate electrode and a source electrode are formed on a second surface opposite to the first surface of the semiconductor chip, and the gate electrode and the source electrode are bonded with metal plate terminalsG,S via connection materials. In addition, the semiconductor chip is sealed by a resin sealing body with mounting-surfaces of the metal plate terminalsG,S being exposed. Mounting surfaces of the metal plate terminalsG,S and a third part of the metal cap are bonded to electrodes on a mounting boardvia connection materialsand

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Gunma, Japan

Hiroi Oka