Nec Corporation

Nec Electronics Corporation

Asm Japan K.k.

Hirohito Watanabe

Toru Tatsumi

Toshiyuki Hirota

Ichiro Honma

Ichiroh Honma

Masanobu Zenke

Motofumi Saitoh

Shintaro Yamamichi

Kiyotaka Imai

Takeshi Okazawa

Naohiko Kimizuka

Hiroki Shirai

Shuji Fujiwara

Fumiki Aiso

Taishi Kubota

Toshiyuki Iwamoto

Mitsusuke Kyogoku

Haruhiko Ono

Yuri Masuoka

Ichirou Honma

Takashi Ogawa

Ken Inoue

Hiroshi Sunamura

Ayuka Tada

Yoichi Miyasaka

Masayuki Terai

Kunihiro Fujii

Makoto Sekine

Toshiyuki Sakuma

Shinji Fujieda

Heiji Watanabe

Sadayuki Ohnishi

Toshiki Hashimoto

Motofumi Saitou

A diffusion layer () is formed in the surface region of a semiconductor substrate (). A control gate electrode () is formed on the substrate. An interlayer dielectric film () covers the entire surface of the substrate. A drain leader line () made of a semiconductor such as n-type polysilicon is led from the drain region, and a source leader line () is led from the source region through the interlayer dielectric film. The drain leader line is surrounded by an annular floating gate (). In erase, for example, the control gate is set to a ground potential, and a positive voltage is applied to the drain leader line to remove electrons in the floating gate to the drain leader line. In write, positive voltages are applied to the control gate electrode and drain leader line to generate CHE and inject hot electrons into the floating gate. This allows to thin the gate insulating film of a flash memory, increase the degree of integration of a nonvolatile memory, and lower the driving voltage.

Nonvolatile semiconductor storage unit and production method therefor

A semiconductor device includes first and second active regions on a semiconductor substrate, separated by an element isolation region; a line-shaped electrode disposed from over the first to over the second active region via the element isolation region; first and second FETs including a gate insulating film on the first and second active regions, respectively, a gate electrode composed of the line-shaped electrode and a source/drain region. Parts of the line-shaped electrode over the first and second active regions are formed of different materials. The line-shaped electrode includes a diffusion restraining region having thickness in a direction perpendicular to the substrate thinner than that over the first and second active regions. The diffusion restraining region is over the element isolation region and spans the whole width of the line-shaped electrode in the gate length direction.

Semiconductor device and manufacturing method thereof

A semiconductor deviceincludes a silicon substrate, an N-type MOSFETincluding a first high dielectric constant filmand a polycrystalline silicon filmon the silicon substrateand a P-type MOSFETincluding a second high dielectric constant filmand a polycrystalline silicon filmjuxtaposed to N-type MOSFETon the silicon substrateThe second high dielectric constant filmis formed to have the film thickness thinner than the film thickness of the first high dielectric constant filmThe first high dielectric constant filmand the second high dielectric constant filmcontains one or more element(s) selected from Hf and Zr.

Semiconductor device having high dielectric constant layers of different thicknesses

The task of the present invention is to enable formation of a gate insulating film structure having a good-quality interface between a silicon oxide film and silicon in an interface between a high dielectric constant thin film and a silicon substrate to provide a semiconductor device and a semiconductor manufacturing method which are capable of improving interface electrical characteristics, which has been a longstanding task in practical use of a high dielectric constant insulating film. A metal layer deposition process and a heat treatment process which supply metal elements constituting a high dielectric constant film on a surface of a base silicon oxide filmallow the metal elements to be diffused into the base silicon oxide filmto thereby form an insulating film structureas a gate insulating film, after forming the base silicon oxide filmon a surface of a silicon substrate. The insulating film structureincluding a silicate region comprises a silicon oxide film region, a silicate region, and a metal rich region, forming a silicate structure having composition modulation in which composition of metal increases as closer to an upper portion, and the composition of silicon increases as closer to a lower portion.

Semiconductor device, production method and production device thereof

A semiconductor devicecomprises a silicon substrate, an N-type MOSFETincluding a high concentration-high dielectric constant filmformed on the silicon substrateand a polycrystalline silicon film, and a P-type MOSFETincluding a low concentration-high dielectric constant filmand a polycrystalline silicon filmformed on the semiconductor substrateto be juxtaposed to the N-type MOSFET. The low concentration-high dielectric constant filmand the high concentration-high dielectric constant filmare composed of a material containing one or more element (s) selected from a group consisting of Hf and Zr. The concentration of the above-described metallic element contained in the low concentration-high dielectric constant filmis lower than that contained in the high concentration-high dielectric constant film

Semiconductor device

A nonvolatile semiconductor memory comprises a silicon substrate, a gate electrode formed through a gate insulator film on a principal surface of the semiconductor substrate, a pair of source/drain regions formed in a principal surface region of the semiconductor substrate to locate the gate electrode between the pair of source/drain regions. The gate insulator film is formed of a silicon oxide and/or silicon nitride film in contact with the principal surface of the semiconductor substrate, and a lead germanate film which is formed on the silicon oxide and/or silicon nitride film and which is a ferroelectric having a dielectric constant of not larger than 50.

Nonvolatile semiconductor memory utilizing polarization of ferroelectric material

After an interlayer insulating film is deposited on a silicon substrate, a contact hole or contact holes is or are formed at a desired position(s) and, then, after a polysilicon layer is deposited and the contact hole(s) is (are) embedded, the surface of the polysilicon layer is flattened by chemical and mechanical polishing using at least one of piperazine or colloidal silica slurry, and a barrier metal film,and a highly dielectric thin film,are deposited and processed to a desired size. Finally, an Al/TiN film,adapted for the upper electrode is formed. The leak current of the thin film capacitor which is obtained according to this method can be greatly reduced.

Method of manufacturing thin film capacitor

In a process of forming hemi-spherical silicon grains on an amorphous silicon film in accordance with the 'crystal nucleation' process, in order to form crystal nuclei on a top surface and a side surface of the amorphous silicon film, SiH.sub.4 is irradiated onto the top and side surfaces of the amorphous silicon film at a stabilized temperature which is lower than, by at least 5.degree. C., an annealing temperature for growing the hemi-spherical silicon grains from the crystal nuclei, with the result that it is possible to suppress or retard the growth of the crystals growing into the amorphous silicon film from a boundary between the amorphous silicon film and an interlayer insulator film. Thereafter, the amorphous silicon film having the crystal nuclei thus formed on the surface thereof is annealed at the annealing temperature so that the hemi-spherical silicon grains are formed on the whole surface of the top and side surfaces of the amorphous silicon film.

Process for forming a capacitor incorporated in a semiconductor device

Ingredient gas is first supplied into a reacting section disposed in an apparatus for chemical vapor deposition. Subsequently, a silicon film is deposited on a wafer under a condition that temperature at the upstream side of a direction of the ingredient gas flow inside the reacting section is higher than that at the downstream side thereof.

Process for producing a semiconductor device having hemispherical grains

The method of manufacturing a semiconductor memory device with a stacked capacitor is disclosed. The method is featured by forming an insulating film on semiconductor substrate, forming a high melting point metal film interposed between capacitor electrode films, selectively etching the capacitor electrode films to expose at least a part of the high melting point metal film, and removing the high melting point metal film by etching using a solution containing at least one selected from sulfuric acid, nitric acid, hydrochloric acid, phosphoric acid, hydrogen peroxide, and ammonia. Thus only the high melting point metal film can be removed without etching the insulating film.

Method of manufacturing a semiconductor memory device with a stacked

Amorphous silicon layers are formed on an n-type single-crystal/poly-crystal layer and a p-type single-crystal/poly-crystal layer, and titanium is sputtered on the amorphous silicon layers; although the n-type dopant impurity are piled on the n-type single-crystal/poly-crystal layers, the amorphous silicon layers takes the piles of n-type dopant impurity thereinto, and promote the silicidation of the titanium layer.

Process of selectively producing refractory metal silicide uniform in

In order to study an etching rate difference of a layer formed mainly with silicon dioxide on a wafer, a thermal oxide film (113) and layers of BSG (117), BPSG (125), and PSG (129) are laminated on a wafer and are etched in a gaseous etching atmosphere consisting essentially of hydrogen fluoride or a mixture of hydrogen fluoride and water vapor. The layers are etched with various etching rates which are higher than that of the thermal oxide film. The etching rate difference is a difference between the etching rate of each layer and an etching rate of the thermal oxide film. The layers may include impurities, such as boron and phosphorus, collectively as a part of a layer material of each layer. The etching rate difference depends on the layer material. Preferably, the gaseous etching atmosphere should have a reduced pressure. Alternatively, a water vapor partial pressure should not be greater than 2000 Pa. As a further alternative, either the layer or the gaseous etching atmosphere should be heated.

Vapor selective etching method and apparatus

In a semiconductor device, such as a memory cell, including a capacitor, a corrugated electrode is used as a lower electrode of the capacitor and is covered with an insulation film to be opposed to an upper electrode. The corrugated electrode is specified in section by a series of folded portions which are alternately folded vertically and horizontally. Practically, the corrugated electrode is formed by a corrugated wall which surrounds a hollow space and which has a rectangular or a polygonal shape on a plane. Alternatively, the corrugated wall has an irregular surface formed by an aggregation of grains so as to effectively widen a surface of the lower electrode. Such a corrugated electrode may be manufactured by a mold which is formed by selectively etching a stack of first-kind spacer films and second-kind spacer films.

Stacked capacitor having a corrugated electrode

A method of forming a silicon layer disclosed herein includes the steps of depositing an amorphous silicon layer on a substrate, irradiating a silane gas to the substrate, and performing an annealing process in a high vacuum or in an inert gas. The amorphous silicon layer is thereby converted into a silicon layer having an uneven surface caused by hemispherical or spherical silicon grains. The annealing process may be performed while irradiating a hydrogen gas or an oxidizing gas. In this case, such a silicon layer that has an even surface is formed.

Method of producing silicon layer having surface controlled to be uneven

There are disclosed a nonvolatile semiconductor memory device, which is capable of maintaining a high capacitance ratio even when a memory cell is formed in a micronized size without increasing the number of manufacturing steps, and its manufacturing method. In a flash memory having buried diffusion layer type cells, a source region and drain regions and are formed in self alignment with a polycrystalline film pattern which has a polycrystalline silicon film having projecting and recessing parts in its upper surface.

Growing community of inventors

Tokyo, Japan

Hirohito Watanabe